SLLSFB6A May   2020  – April 2021 DRV8705-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8705-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Low-Side Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.2 CONTROL Registers

Table 7-19 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.

Table 7-19 CONTROL Registers
AddressAcronymRegister NameSection
4hIC_CTRLIC control registerGo
5hBRG_CTRLBRG control registerGo
6hDRV_CTRL_1DRV control register 1Go
7hDRV_CTRL_2DRV control register 2Go
8hDRV_CTRL_3DRV control register 3Go
9hVDS_CTRL_1VDS control register 1Go
AhVDS_CTRL_2VDS control register 2Go
BhOLSC_CTRLOLSC control registerGo
ChUVOV_CTRLUVOV control registerGo
DhCSA_CTRLCSA control registerGo

Complex bit access types are encoded to fit into small table cells. Table 7-20 shows the codes that are used for access types in this section.

Table 7-20 CONTROL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.2.1 IC_CTRL Register (Address = 4h) [reset = 6h]

IC_CTRL is shown in Figure 7-31 and described in Table 7-21.

Return to Summary Table.

Control register for IC configurations

Figure 7-31 IC_CTRL Register
76543210
EN_DRVSSC_DISIN1/EN_MODEIN2/PH_MODELOCKCLR_FLT
R/W-0bR/W-0bR/W-0bR/W-0bR/W-11bR/W-0b
Table 7-21 IC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7EN_DRVR/W0bEnable gate driver bit

0b = Driver inputs are ignored and the gate driver passive pulldowns are enabled.

1b = Gate driver outputs are enabled and controlled by the digital inputs.

6SSC_DISR/W0bDisable device spread spectrum clocking

0b = Enabled.

1b = Disabled.

5IN1/EN_MODER/W0bIN1/EN control mode.

0b = IN1/EN signal is sourced from the IN1/EN pin.

1b = IN1/EN signal is sourced from the S_IN1/EN bit.

4IN2/PH_MODER/W0bIN2/PH control mode.

0b = IN2/PH signal is sourced from the IN2/PH pin.

1b = IN2/PH signal is sourced from the S_IN2/PH bit.

3-1LOCKR/W11bLock and unlock the control registers. Bit settings not listed have no effect.

011b = Unlock all control registers.

110b = Lock the control registers by ignoring further writes except to these bits.

0CLR_FLTR/W0bClear latched fault status information.

0b = Default state.

1b = Clear faults, resets to 0b after completion.

7.6.2.2 BRG_CTRL Register (Address = 5h) [reset = 0h]

BRG_CTRL is shown in Figure 7-32 and described in Table 7-22.

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Control register for bridge configurations and output control

Figure 7-32 BRG_CTRL Register
76543210
VGS_HS_DISBRG_MODEBRG_FWS_IN1/ENS_IN2/PHS_HIZ1S_HIZ2
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-22 BRG_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7VGS_HS_DISR/W0bVGS monitor based dead-time handshake.

0b = Enabled.

1b = Disabled. Gate drive transition based on tDRIVE and tDEAD time duration.

6-5BRG_MODER/W00bH-bridge input control mode.

00b = Independent half-bridge input control.

01b = PH/EN H-bridge input control.

10b = PWM H-bridge input control.

11b = Split HS/LS solenoid input control.

4BRG_FWR/W0bH-bridge control freewheeling setting.

0b = Low-side freewheeling.

1b = High-side freewheeling.

3S_IN1/ENR/W0bControl bit for IN1/EN input signal. Enabled through IN1/EN_MODE bit.
2S_IN2/PHR/W0bControl bit for IN2/PH input signal. Enabled through IN2/PH_MODE bit.
1S_HIZ1R/W0bControl bit for HIZ1 input signal. Logic OR with the nHIZ1 pin. Active only in half-bridge input control mode.

0b = Outputs follow IN1/EN signal.

1b = Gate drivers pulldowns are enabled. Half-bridge 1 Hi-Z

0S_HIZ2R/W0bControl bit for HIZ2 input signal. Logic OR with the nHIZ2 pin. Active only in half-bridge input control mode.

0b = Outputs follow IN2/PH signal.

1b = Gate drivers pulldowns are enabled. Half-bridge 2 Hi-Z

7.6.2.3 DRV_CTRL_1 Register (Address = 6h) [reset = FFh]

DRV_CTRL_1 is shown in Figure 7-33 and described in Table 7-23.

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Control register for DRV gate current configuration

Figure 7-33 DRV_CTRL_1 Register
76543210
IDRVP_HSIDRVN_HS
R/W-1111bR/W-1111b
Table 7-23 DRV_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-4IDRVP_HSR/W1111bHigh-side peak source pull up current.

0000b = 0.5 mA

0001b = 1 mA

0010b = 2 mA

0011b = 3 mA

0100b = 4 mA

0101b = 6 mA

0110b = 8 mA

0111b = 12 mA

1000b = 16 mA

1001b = 20 mA

1010b = 24 mA

1011b = 28 mA

1100b = 31 mA

1101b = 40 mA

1110b = 48 mA

1111b = 62 mA

3-0IDRVN_HSR/W1111bHigh-side peak sink pull down current.

0000b = 0.5 mA

0001b = 1 mA

0010b = 2 mA

0011b = 3 mA

0100b = 4 mA

0101b = 6 mA

0110b = 8 mA

0111b = 12 mA

1000b = 16 mA

1001b = 20 mA

1010b = 24 mA

1011b = 28 mA

1100b = 31 mA

1101b = 40 mA

1110b = 48 mA

1111b = 62 mA

7.6.2.4 DRV_CTRL_2 Register (Address = 7h) [reset = FFh]

DRV_CTRL_2 is shown in Figure 7-34 and described in Table 7-24.

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Control register for DRV gate current configuration

Figure 7-34 DRV_CTRL_2 Register
76543210
IDRVP_LSIDRVN_LS
R/W-1111bR/W-1111b
Table 7-24 DRV_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-4IDRVP_LSR/W1111bLow-side peak source pull up current.

0000b = 0.5 mA

0001b = 1 mA

0010b = 2 mA

0011b = 3 mA

0100b = 4 mA

0101b = 6 mA

0110b = 8 mA

0111b = 12 mA

1000b = 16 mA

1001b = 20 mA

1010b = 24 mA

1011b = 28 mA

1100b = 31 mA

1101b = 40 mA

1110b = 48 mA

1111b = 62 mA

3-0IDRVN_LSR/W1111bLow-side peak sink pull down current.

0000b = 0.5 mA

0001b = 1 mA

0010b = 2 mA

0011b = 3 mA

0100b = 4 mA

0101b = 6 mA

0110b = 8 mA

0111b = 12 mA

1000b = 16 mA

1001b = 20 mA

1010b = 24 mA

1011b = 28 mA

1100b = 31 mA

1101b = 40 mA

1110b = 48 mA

1111b = 62 mA

7.6.2.5 DRV_CTRL_3 Register (Address = 8h) [reset = 20h]

DRV_CTRL_3 is shown in Figure 7-35 and described in Table 7-25.

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Control register for DRV dead-time, gate current drive time, and VDS blanking time

Figure 7-35 DRV_CTRL_3 Register
76543210
VGS_MODEVGS_TDRVVGS_TDEADVGS_IND
R/W-00bR/W-10bR/W-000bR/W-0b
Table 7-25 DRV_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
7-6VGS_MODER/W00bVGS gate fault monitor mode.

00b = Latched fault.

01b = Cycle by cycle.

10b = Warning report only.

11b = Disabled.

5-4VGS_TDRVR/W10bVGS drive time and VDS monitor blanking time.

00b = 96 µs

01b = 2 µs

10b = 4 µs

11b = 8 µs

3-1VGS_TDEADR/W000bInsertable digital dead-time.

000b = 0 ns

001b = 250 ns

010b = 500 ns

011b = 750 ns

100b = 1000 ns

101b = 2000 ns

110b = 4000 ns

111b = 8000 ns

0VGS_INDR/W0bVGS independent shutdown mode enable. Active for BRG_MODE = 00b, 11b.

0b = Disabled.

1b = Enabled. VGS gate fault will only shutdown the associated half-bridge.

7.6.2.6 VDS_CTRL_1 Register (Address = 9h) [reset = 20h]

VDS_CTRL_1 is shown in Figure 7-36 and described in Table 7-26.

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Control register for VDS overcurrent comparators

Figure 7-36 VDS_CTRL_1 Register
76543210
VDS_MODEVDS_DGVDS_IDRVNVGS_LVLVDS_IND
R/W-00bR/W-10bR/W-00bR/W-0bR/W-0b
Table 7-26 VDS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
7-6VDS_MODER/W00bVDS overcurrent monitor mode.

00b = Latched fault.

01b = Cycle by cycle.

10b = Warning report only.

11b = Disabled.

5-4VDS_DGR/W10bVDS overcurrent monitor deglitch time.

00b = 1 µs

01b = 2 µs

10b = 4 µs

11b = 8 µs

3-2VDS_IDRVNR/W00bIDRVN gate pulldown current after VDS_OCP fault.

00b = Programmed IDRVN

01b = 8 mA

10b = 31 mA

11b = 62 mA

1VGS_LVLR/W0bVGS monitor threshold for dead-time handshake and gate fault detection.

0b = 1.4 V.

1b = 1.0 V

0VDS_INDR/W0bVDS independent shutdown mode enable. Active for BRG_MODE = 00b, 11b.

0b = Disabled.

1b = Enabled. VDS overcurrent fault will only shutdown the associated half-bridge.

7.6.2.7 VDS_CTRL_2 Register (Address = Ah) [reset = DDh]

VDS_CTRL_2 is shown in Figure 7-37 and described in Table 7-27.

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Control register for VDS threshold voltage

Figure 7-37 VDS_CTRL_2 Register
76543210
VDS_HS_LVLVDS_LS_LVL
R/W-1101bR/W-1101b
Table 7-27 VDS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
7-4VDS_HS_LVLR/W1101bHigh-side VDS overcurrent monitor threshold.

0000b = 0.06 V

00001b = 0.08 V

0010b = 0.10 V

0011b = 0.12 V

0100b = 0.14 V

0101b = 0.16 V

0110b = 0.18 V

0111b = 0.2 V

1000b = 0.3 V

1001b = 0.4 V

1010b = 0.5 V

1011b = 0.6 V

1100b = 0.7 V

1101b = 1 V

1110b = 1.4 V

1111b = 2 V

3-0VDS_LS_LVLR/W1101bLow-side VDS overcurrent monitor threshold.

0000b = 0.06 V

0001b = 0.08 V

0010b = 0.10 V

0011b = 0.12 V

0100b = 0.14 V

0101b = 0.16 V

0110b = 0.18 V

0111b = 0.2 V

1000b = 0.3 V

1001b = 0.4 V

1010b = 0.5 V

1011b = 0.6 V

1100b = 0.7 V

1101b = 1 V

1110b = 1.4 V

1111b = 2 V

7.6.2.8 OLSC_CTRL Register (Address = Bh) [reset = 0h]

OLSC_CTRL is shown in Figure 7-38 and described in Table 7-28.

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Control register of offline diagnostics.

Figure 7-38 OLSC_CTRL Register
76543210
RESERVEDOLSC_ENPU_SH1PD_SH1PU_SH2PD_SH2
R/W-000bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-28 OLSC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W000bReserved
4OLSC_ENR/W0bOffline open load and short circuit diagnostic enable.

0b = Disabled.

1b = VDS monitors set into real-time voltage monitor mode and diagnostics current sources enabled.

3PU_SH1R/W0bHalf-bridge 1 pull up diagnostic current source. Must set OLSC_EN bit to use.

0b = Disabled.

1b = Enabled.

2PD_SH1R/W0bHalf-bridge 1 pull down diagnostic current source. Must set OLSC_EN bit to use.

0b = Disabled.

1b = Enabled.

1PU_SH2R/W0bHalf-bridge 2 pull up diagnostic current source. Must set OLSC_EN bit to use.

0b = Disabled.

1b = Enabled.

0PD_SH2R/W0bHalf-bridge 2 pull down diagnostic current source. Must set OLSC_EN bit to use.

0b = Disabled.

1b = Enabled.

7.6.2.9 UVOV_CTRL Register (Address = Ch) [reset = 14h]

UVOV_CTRL is shown in Figure 7-39 and described in Table 7-29.

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Control register for undervoltage and overvoltage monitors

Figure 7-39 UVOV_CTRL Register
76543210
PVDD_UV_MODEPVDD_OV_MODEPVDD_OV_DGPVDD_OV_LVLVCP_UV_MODEVCP_UV_LVL
R/W-0bR/W-00bR/W-10bR/W-1bR/W-0bR/W-0b
Table 7-29 UVOV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7PVDD_UV_MODER/W0bPVDD supply undervoltage monitor mode.

0b = Latched fault.

1b = Automatic recovery.

6-5PVDD_OV_MODER/W00bPVDD supply overvoltage monitor mode.

00b = Latched fault.

01b = Automatic recovery.

10b = Warning report only.

11b = Disabled.

4-3PVDD_OV_DGR/W10bPVDD supply overvoltage monitor deglitch time.

00b = 1 µs

01b = 2 µs

10b = 4 µs

11b = 8 µs

2PVDD_OV_LVLR/W1bPVDD supply overvoltage monitor threshold.

0b = 21.5 V

1b = 28.5 V

1VCP_UV_MODER/W0bVCP charge pump undervoltage monitor mode.

0b = Latched fault.

1b = Automatic recovery.

0VCP_UV_LVLR/W0bVCP charge pump undervoltage monitor threshold.

0b = 2.5 V

1b = 5 V

7.6.2.10 CSA_CTRL Register (Address = Dh) [reset = 1h]

CSA_CTRL is shown in Figure 7-40 and described in Table 7-30.

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Control register for current shunt amplifier

Figure 7-40 CSA_CTRL Register
76543210
CSA_SH_ENCSA_BLK_SELCSA_BLKCSA_DIVCSA_GAIN
R/W-0bR/W-0bR/W-000bR/W-0bR/W-01b
Table 7-30 CSA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7CSA_SH_ENR/W0bCurrent shunt amplifier sample and hold.

0b = Disabled

1b = Enabled

6CSA_BLK_SELR/W0bCurrent shunt amplifier blanking trigger source.

0b = Half-bridge 1

1b = Half-bridge 2

5-3CSA_BLKR/W000bCurrent shunt amplifier blanking time. % of tDRV.

000b = 0 %, Disabled

001b = 25 %

010b = 37.5 %

011b = 50 %

100b = 62.5 %

101b = 75 %

110b = 87.5 %

111b = 100 %

2CSA_DIVR/W0bCurrent shunt amplifier reference voltage divider.

0b = AREF / 2

1b = AREF / 8

1-0CSA_GAINR/W01bCurrent shunt amplifier gain setting.

00b = 10 V/V

01b = 20 V/V

10b = 40 V/V

11b = 80 V/V