SLLSFB6A May 2020 – April 2021 DRV8705-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The table below lists the memory-mapped registers for the device. All register addresses not listed should be considered as reserved locations and the register contents should not be modified. Descriptions of reserved locations are provided for reference only.
Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Type | Address |
---|---|---|---|---|---|---|---|---|---|---|
IC_STAT_1 | SPI_OK | POR | FAULT | WARN | DS_GS | UV | OV | OT | R | 0h |
VGS_VDS_STAT | VGS_H1 | VGS_L1 | VGS_H2 | VGS_L2 | VDS_H1 | VDS_L1 | VDS_H2 | VDS_L2 | R | 1h |
IC_STAT_2 | PVDD_UV | PVDD_OV | VCP_UV | OTW | OTSD | RSVD | SCLK_FLT | ADDR_FLT | R | 2h |
RSVD_STAT | RSVD | R | 3h | |||||||
IC_CTRL | EN_DRV | SSC_DIS | IN1/EN_MODE | IN2/PH_MODE | LOCK | CLR_FLT | R/W | 4h | ||
BRG_CTRL | VGS_HS_DIS | BRG_MODE | BRG_FW | S_IN1/EN | S_IN2/PH | S_HIZ1 | S_HIZ2 | R/W | 5h | |
DRV_CTRL_1 | IDRVP_HS | IDRVN_HS | R/W | 6h | ||||||
DRV_CTRL_2 | IDRVP_LS | IDRVN_LS | R/W | 7h | ||||||
DRV_CTRL_3 | VGS_MODE | VGS_TDRV | VGS_TDEAD | VGS_IND | R/W | 8h | ||||
VDS_CTRL_1 | VDS_MODE | VDS_DG | VDS_IDRVN | VGS_LVL | VDS_IND | R/W | 9h | |||
VDS_CTRL_2 | VDS_HS_LVL | VDS_LS_LVL | R/W | Ah | ||||||
OLSC_CTRL | RSVD | OLSC_EN | PU_SH1 | PD_SH1 | PU_SH2 | PD_SH2 | R/W | Bh | ||
UVOV_CTRL | PVDD_UV_MODE | PVDD_OV_MODE | PVDD_OV_DG | PVDD_OV_LVL | VCP_UV_MODE | VCP_UV_LVL | R/W | Ch | ||
CSA_CTRL | CSA_SH_EN | CSA_BLK_SEL | CSA_BLK | CSA_DIV | CSA_GAIN | R/W | Dh |