SLVSCC0D November 2013 – October 2019 DRV8850
The DRV8850 internal logic and charge pump are operating unless nSLEEP is pulled low. The LDO regulator can be active independent of the nSLEEP pin. This independence allows a microcontroller or other device to be powered by the LDO regulator while retaining the ability to put the DRV8850 into sleep mode.
If LDOEN and nSLEEP are both brought logic low the device will minimize current consumption in sleep mode. While the LDO regulator remains active n sleep mode, a quiescent current (typically 50 µA plus current through the external feedback resistors) is drawn from the supply.
Each FET inside the device is controlled by a corresponding input pin on the DRV8850. The condition where both HS and LS FETs are turned on at the same time is not allowed. During this input condition both the HS and LS FETs turn off.