SLVSDY7B October   2017  – January 2021 DRV8873-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 22
        4. 7.3.1.4 Internal Current Sense and Current Regulation
        5. 7.3.1.5 Slew-Rate Control
        6. 7.3.1.6 Dead Time
        7. 7.3.1.7 Propagation Delay
        8. 7.3.1.8 nFAULT Pin
        9. 7.3.1.9 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PINTYPE(4)DESCRIPTION
NAMENO.
DRV8873H-Q1DRV8873S-Q1
CPH2222PWRCharge pump switching node. Connect a X7R capacitor with a value of 47 nF between the CPH and CPL pins.
CPL2323PWRCharge pump switching node. Connect a X7R capacitor with a value of 47 nF between the CPH and CPL pins.
DVDD11PWRDigital regulator. This pin is the 5-V internal digital-supply regulator. Bypass this pin to GND with a 6.3-V, 1-µF ceramic capacitor.
EN/IN177IControl Inputs. For details, see the Section 7.3.1.1 section. This pin has an internal pulldown resistor to GND.
DISABLE99IBridge disable input. A logic high on this pin disables the H-bridge Hi-Z. Internal pullup to DVDD.
GND2424PWRGround pin
IPROPI11010OHigh-side FET current. The analog current proportional to the current flowing in the half bridge.
IPROPI21212OHigh-side FET current. The analog current proportional to the current flowing in the half bridge.
nITRIP5—IInternal current-regulation control pin (ITRIP). To enable the ITRIP feature, do not connect this pin (or tie it to GND). To disable the ITRIP feature, connect this pin to the DVDD pin.
nOL6—IOpen-load diagnostic control pin. To run the open-load diagnostic at power up, tie it to ground. Connect it to DVDD, open-load diagnostic will be disabled.
MODE3—IInput mode pin. Sets the PH/EN, PWM, or independent-PWM mode.
OUT11818OHalf-bridge output 1. Connect this pin to the motor or load.
OUT11919OHalf-bridge output 1. Connect this pin to the motor or load.
OUT21414OHalf-bridge output 2. Connect this pin to the motor or load.
OUT21515OHalf-bridge output 2. Connect this pin to the motor or load.
PH/IN288IControl inputs. For details, see the Section 7.3.1.1 section. This pin has an internal pulldown resistor to GND.
SCLK—5ISerial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI—4ISerial data input. Data is captured on the falling edge of the SCLK pin.
SDO—3PPSerial data output. Data is shifted out on the rising edge of the SCLK pin. This is a push-pull output.
SR4—ISlew rate adjust. This pin sets the slew rate of the H-bridge outputs.
SRC1616OPower FET source. Tie this pin to GND through a low-impedance path.
SRC1717OPower FET source. Tie this pin to GND through a low-impedance path.
VCP2121PWRCharge pump output. Connect a 16-V, 1-µF ceramic capacitor from this pin to the VM supply.
VM1313PWRPower supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor.
VM2020PWRPower supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor.
nFAULT22ODFault indication pin. This pin is pulled logic low with a fault condition. This open-drain output requires an external pullup resistor.
nSCS—6ISerial chip select. An active low on this pin enables the serial interface communications. Internal pullup to nSLEEP.
nSLEEP1111ISleep input. To enter a low-power sleep mode, set this pin logic low.
(4) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output, PP = push-pull output