SLVSDY7B October 2017 – January 2021 DRV8873-Q1
PRODUCTION DATA
Table 7-18 lists the memory-mapped registers for the device. All register addresses not listed in Table 7-18 should be considered as reserved locations and the register contents should not be modified.
Register Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Access Type | Address |
---|---|---|---|---|---|---|---|---|---|---|
FAULT Status | RSVD | FAULT | OTW | UVLO | CPUV | OCP | TSD | OLD | R | 0x00 |
DIAG Status | OL1 | OL2 | ITRIP1 | ITRIP2 | OCP_H1 | OCP_L1 | OCP_H2 | OCP_L2 | R | 0x01 |
IC1 Control | TOFF | SPI_IN | SR | MODE | RW | 0x02 | ||||
IC2 Control | ITRIP_REP | TSD_MODE | OTW_REP | DIS_CPUV | OCP_TRETRY | OCP_MODE | RW | 0x03 | ||
IC3 Control | CLR_FLT | LOCK | OUT1_DIS | OUT2_DIS | EN_IN1 | PH_IN2 | RW | 0x04 | ||
IC4 Control | RSVD | EN_OLP | OLP_DLY | EN_OLA | ITRIP_LVL | DIS_ITRIP | RW | 0x05 |
Complex bit access types are encoded to fit into small table cells. Table 7-19 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
The status registers are used to reporting warning and fault conditions. Status registers are read-only registers
Table 7-20 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-20 should be considered as reserved locations and the register contents should not be modified.
FAULT status is shown in Figure 7-23 and described in Table 7-21.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | FAULT | OTW | UVLO | CPUV | OCP | TSD | OLD |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RSVD | R | 0b | Reserved |
6 | FAULT | R | 0b | Global FAULT status register. Compliments the nFAULT pin |
5 | OTW | R | 0b | Indicates overtemperature warning |
4 | UVLO | R | 0b | Indicates UVLO fault condition |
3 | CPUV | R | 0b | Indicates charge-pump undervoltage fault condition |
2 | OCP | R | 0b | Indicates an overcurrent condition |
1 | TSD | R | 0b | Indicates an overtemperature shutdown |
0 | OLD | R | 0b | Indicates an open-load detection |
DIAG status is shown in Figure 7-24 and described in Table 7-22.
Read-only
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OL1 | OL2 | ITRIP1 | ITRIP2 | OCP_H1 | OCP_L1 | OCP_H2 | OCP_L2 |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | OL1 | R | 0b | Indicates open-load detection on half bridge 1 |
6 | OL2 | R | 0b | Indicates open-load detection on half bridge 2 |
5 | ITRIP1 | R | 0b | Indicates the current regulation status of half bridge 1. 0b = Indicates output 1 is not in current regulation 1b = Indicates output 1 is in current regulation |
4 | ITRIP2 | R | 0b | Indicates the current regulation status of half bridge 2. 0b = Indicates output 2 is not in current regulation 1b = Indicates output 2 is in current regulation |
3 | OCP_H1 | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 1 |
2 | OCP_L1 | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 1 |
1 | OCP_H2 | R | 0b | Indicates overcurrent fault on the high-side FET of half bridge 2 |
0 | OCP_L2 | R | 0b | Indicates overcurrent fault on the low-side FET of half bridge 2 |
The IC control registers are used to configure the device. Status registers are read and write capable.
Table 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 7-23 should be considered as reserved locations and the register contents should not be modified.
IC1 control is shown in Figure 7-25 and described in Table 7-24.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOFF | SPI_IN | SR | MODE | ||||
R/W-01b | R/W-0b | R/W-100b | R/W-01b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7-6 | TOFF | R/W | 01b | 00b = 20 µs 01b = 40 µs 10b = 60 µs 11b = 80 µs |
5 | SPI_IN | R/W | 0b | 0b = Outputs follow input pins (INx) 1b = Outputs follow SPI registers EN_IN1 and PH_IN2 |
4-2 | SR | R/W | 100b | 000b = 53.2-V/µs rise time 001b = 34-V/µs rise time 010b = 18.3-V/µs rise time 011b = 13-V/µs rise time 100b = 10.8-V/µs rise time 101b = 7.9-V/µs rise time 110b = 5.3-V/µs rise time 111b = 2.6-V/µs rise time |
1-0 | MODE | R/W | 01b | 00b = PH/EN 01b = PWM 10b = Independent half bridge 11b = Input disabled; bridge Hi-Z |
IC2 control is shown in Figure 7-26 and described in Table 7-25.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ITRIP_REP | TSD_MODE | OTW_REP | DIS_CPUV | OCP_TRETRY | OCP_MODE | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-11b | R/W-00b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | ITRIP_REP | R/W | 0b | 0b = ITRIP is not reported on nFAULT or the FAULT bit 1b = ITRIP is reported on nFAULT and the FAULT bit |
6 | TSD_MODE | R/W | 0b | 0b = Overtemperature condition causes a latched fault 1b = Overtemperature condition causes an automatic recovery fault |
5 | OTW_REP | R/W | 0b | 0b = OTW is not reported on nFAULT or the FAULT bit 1b = OTW is reported on nFAULT and the FAULT bit |
4 | DIS_CPUV | R/W | 0b | 0b = Charge pump undervoltage fault is enabled 1b = Charge pump undervoltage fault is disabled |
3-2 | OCP_TRETRY | R/W | 11b | 00b = Overcurrent retry time is 0.5 ms 01b = Overcurrent retry time is 1 ms 10b = Overcurrent retry time is 2 ms 11b = Overcurrent retry time is 4 ms |
1-0 | OCP_MODE | R/W | 00b | 00b = Overcurrent condition causes a latched fault 01b = Overcurrent condition causes an automatic retrying fault 10b = Overcurrent condition is report only but no action is taken 11b = Overcurrent condition is not reported and no action is taken |
IC3 control is shown in Figure 7-27 and described in Table 7-26.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR_FLT | LOCK | OUT1_DIS | OUT2_DIS | EN_IN1 | PH_IN2 | ||
R/W-0b | R/W-100b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | CLR_FLT | R/W | 0b | Write a 1b to this bit to clear the fault bits. This bit is automatically reset after a write. |
6-4 | LOCK | R/W | 100b | Write 011b to this register to lock all register settings in the IC1 control register except to these bits and address 0x04, bit 7 (CLR_FLT) |
3 | OUT1_DIS | R/W | 0b | Enabled only in the Independent PWM mode 0b = Half bridge 1 enabled 1b = Half bridge 1 disabled (Hi-Z) |
2 | OUT2_DIS | R/W | 0b | Enabled only in the Independent PWM mode 0b = Half bridge 2 enabled 1b = Half bridge 2 disabled (Hi-Z) |
1 | EN_IN1 | R/W | 0b | EN/IN1 bit to control the outputs through SPI (when SPI_IN = 1b) |
0 | PH_IN2 | R/W | 0b | PH/IN2 bit to control the outputs through SPI (when SPI_IN = 1b) |
IC4 control is shown in Figure 7-28 and described in Table 7-27.
Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | EN_OLP | OLP_DLY | EN_OLA | ITRIP_LVL | DIS_ITRIP | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-10b | R/W-00b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RSVD | R/W | 0b | Reserved |
6 | EN_OLP | R/W | 0b | Write 1b to run open load diagnostic in standby mode. When open load test is complete EN_OLP returns to 0b (status check) |
5 | OLP_DLY | R/W | 0b | 0b = Open load diagnostic delay is 300 µs 1b = Open load diagnostic delay is 1.2 ms |
4 | EN_OLA | R/W | 0b | 0b = Open load diagnostic in active mode is disabled 1b = Enable open load diagnostics in active mode |
3-2 | ITRIP_LVL | R/W | 10b | 00b = 4 A 01b = 5.4 A 10b = 6.5 A 11b = 7 A |
1-0 | DIS_ITRIP | R/W | 00b | 00b = Current regulation is enabled 01b = Current regulation is disabled for OUT1 10b = Current regulation is disabled for OUT2 11b = Current regulation is disabled for both OUT1 and OUT2 |