SLOSE62A January   2021  – May 2022 DRV8935

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control and Current Regulation
      2. 7.3.2 Decay Modes
        1. 7.3.2.1 Blanking time
      3. 7.3.3 Charge Pump
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Quad-Level Pin Diagrams
      6. 7.3.6 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5. 7.3.7.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4. 7.4.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
      3. 8.2.3 Power Dissipation Calculation and Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Bridge Control and Current Regulation

The INx input pins directly control the state (high or low) of the OUTx outputs. The truth table is shown below.

Table 7-2 DRV8935 Control Interface
nSLEEPINxOUTxDESCRIPTION
0XHi-ZSleep mode; Half-bridge disabled (Hi-Z)
10LOUTx Low-side ON
11HOUTx High-side ON

When an output load is connected to the VM supply, the load current can be regulated to the ITRIP level. The ITRIP current level for OUT1 and OUT2 outputs is controlled by the VREF12 pin, and the ITRIP level for OUT3 and OUT4 outputs is controlled by the VREF34 pin. The ITRIP current (ITRIP) can be calculated as ITRIP (A) = VREF (V) / 1.32 (V/A). The VREF voltage can be programmed by connecting resistor dividers from DVDD pin to ground. Both VREF pins can be tied together to program the same ITRIP current for all four output channels.

The DRV8935 can simultaneously drive four resistive or inductive loads connected to VM supply. With INx = 0, the low side FET is turned ON till the current increases and hits the ITRIP level. Once the load current equals ITRIP, the low-side FET is turned OFF and the high-side FET is turned on for a period of off-time determined by the TOFF pin. After the off-time expires, the low-side FET is again turned ON and the cycle repeats. The OFF time settings can be changed on the fly. After a OFF time setting change, the new OFF time is applied after a 10 µs de-glitch time.

For resistive loads connected to VM, if the ITRIP is higher than the (VM / RLOAD), the load current is regulated at VM / RLOAD level while INx = 0. For inductive loads connected to VM, it should be ensured that the current decays enough every cycle to prevent runaway and triggering overcurrent protection. The different scenarios are shown below -

GUID-44C45C07-4703-4E0D-8BF1-B99CE56A3C9F-low.gifFigure 7-3 Resistive Load Connected to VM, Cycle-by-cycle control, ITRIP is higher than VM/RLOAD.
GUID-BB81C6FB-C6DD-49A2-97CE-9BF479FABC24-low.gifFigure 7-4 Inductive Load Connected to VM, fixed off-time current chopping
In this scenario, with INx = 0, the high-side MOSFET is turned on for tOFF duration after IOUT exceeds ITRIP. After tOFF, the low side MOSFET is again turned on till IOUT exceeds ITRIP again. The fixed off-time mode allows for a simple current chopping scheme without involvement from the external controller. Fixed off-time mode will support 100% duty cycle current regulation.

Another way of controlling the load current is the cycle-by-cycle control mode, where PWM pulse width of the INx input pins are controlled. This allows for additional control of the current chopping scheme by the external controller. For loads connected to VM, when INx = 0, the current through the load builds up; and when INx = 1, the current through the load decays. By properly choosing the duty cycle of the INx pulse, current can be regulated to a target value. Various such scenarios are shown below -

GUID-DBE0A1C9-002D-481F-9FED-C7B8BD8E80D7-low.gifFigure 7-5 Inductive Load Connected to VM, Cycle-by-cycle control
This scenarion requires INx pin duty cycle adjustment to ensure that the current does not run away.
GUID-20A05478-F0EE-42B2-BB63-689FFE637CA6-low.gifFigure 7-6 Inductive Load Connected to VM, Cycle-by-cycle control, T has to be less than TOFF of the DRV8935.
Similarly, current through loads connected to ground can be controlled by controlling the INx pin pulse width - INx = 1 builds up the current, and INx = 0 decays the current. Two such scenarios are shown below -

GUID-657F89DD-DBE9-4C84-843D-D0A6C7949EF0-low.gifFigure 7-7 Inductive Load Connected to ground, Cycle-by-cycle control
This scenario requires INx pin duty cycle adjustment to ensure that the current does not run away.
GUID-5ACB60E4-D62F-4C81-9897-2D2826FD78FB-low.gifFigure 7-8 Resistive Load Connected to ground, Cycle-by-cycle control.