SNLS507C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   Features
  2. 1Applications
  3. 2Description
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.7 Recommended Timing for the Serial Control Bus

Over I2C supply and temperature ranges unless otherwise specified.
MINMAXUNIT
I2C SERIAL CONTROL BUS (Figure 4-4)
fSCLSCL Clock FrequencyStandard-mode>0100kHz
Fast-mode>0400
Fast-mode Plus>01000
tLOWSCL Low PeriodStandard-mode4.7µs
Fast-mode1.3
Fast-mode Plus0.5
tHIGHSCL High PeriodStandard-mode4µs
Fast-mode0.6
Fast-mode Plus0.26
tHD;STAHold time for a start or a repeated start conditionStandard-mode4µs
Fast-mode0.6
Fast-mode Plus0.26
tSU;STASet Up time for a start or a repeated start conditionStandard-mode4.7µs
Fast-mode0.6
Fast-mode Plus0.26
tHD;DATData Hold TimeStandard-mode0µs
Fast-mode0
Fast-mode Plus0
tSU;DATData Set Up TimeStandard-mode250ns
Fast-mode100
Fast-mode Plus50
tSU;STOSet Up Time for STOP ConditionStandard-mode4µs
Fast-mode0.6
Fast-mode Plus0.26
tBUFBus Free Time Between STOP and STARTStandard-mode4.7µs
Fast-mode1.3
Fast-mode Plus0.5
trSCL and SDA Rise TimeStandard-mode1000ns
Fast-mode300
Fast-mode Plus120
tfSCL and SDA Fall TimeStandard-mode300ns
Fast-mode300
Fast-mode Plus120
CbCapacitive Load for Each Bus Line(1)Standard-mode400pF
Fast-mode400
Fast-mode Plus550
tSPInput Filter(1)Fast-mode50ns
Fast-mode Plus50
(1) Specification is ensured by design and/or characterization and is not tested in production.
GUID-2DF67492-EC81-4C2E-908C-892A847671A8-low.gifFigure 4-1 LVCMOS Transition Times
GUID-3190A2AB-A114-44CE-8C15-624EB436B450-low.gifFigure 4-2 FPD-Link III Receiver VID, VIN, VCM
GUID-97CA50C6-278F-4744-88FF-992FB8B197B3-low.gifFigure 4-3 Deserializer Data Lock Time
GUID-66342DFE-CD7A-4A73-9073-78BC10B1CFEA-low.gifFigure 4-4 I2C Serial Control Bus Timing
GUID-642947D0-BC9D-40DA-A1A4-30D1D8409EF5-low.gifFigure 4-5 SSO Test Pattern for Power Consumption
GUID-3099FCA6-6E4C-44FE-B2A6-FDA69D8A8DA9-low.gifFigure 4-6 Deserializer Delay
GUID-8A9A09B1-DC02-4F35-A1BA-39B9199AED14-low.gifFigure 4-7 Deserializer Output Setup/Hold Times
GUID-A6DD7929-2EE2-4A2B-93E1-8E0BDAAC7083-low.gifFigure 4-8 Output State (Setup and Hold) Times
GUID-1A938CC7-61E6-498A-A705-E240B1CAA3A3-low.gifFigure 4-9 Spread Spectrum Clock Output Profile