SNLS507C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   Features
  2. 1Applications
  3. 2Description
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Support Resources
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
LVCMOS I/O
tRCPReceiver Output Clock Period.
See Figure 4-7.		10-bit ModePCLK, 50 - 100 MHz1020ns
12-bit HF ModePCLK, 37.5 - 100 MHz1026.7
12-bit LF ModePCLK, 25 - 50 MHz2040
tPDCPCLK Duty Cycle(1)10-bit ModePCLK45%50%55%
12-bit HF or LF Mode40%50%60%
tCLHLVCMOS Low-to-High Transition Time(1)
See Figure 4-1.		V(VDDIO) = 1.71 V to 1.89 V
OR
V(VDDIO) = 3.0 V to 3.6 V
CL = 8 pF (lumped load)
Default Registers		PCLK22.8ns
tCHLLVCMOS High-to-Low Transition Time(1)
See Figure 4-1.		PCLK22.8ns
tCLHLVCMOS Low-to-High Transition Time(1)
See Figure 4-1.		ROUT[11:0], HSYNC, VSYNC, GPIO[2:0]23ns
tCHLLVCMOS High-to-Low Transition Time(1)
See Figure 4-1.		ROUT[11:0], HSYNC, VSYNC, GPIO[2:0]23ns
tROSROUT Setup Data to PCLK(1)
See Figure 4-7.		PCLK, ROUT[11:0], HSYNC, VSYNC0.38T0.5Tns
tROHROUT Hold Data to PCLK(1)
See Figure 4-7.		PCLK, ROUT[11:0], HSYNC, VSYNC0.38T0.5Tns
tDDDeserializer Delay(1)
See Figure 4-6.		Default Registers (RRFB = 1)10-bit mode175T185Tns
12-bit HF mode100T115T
12-bit LF mode65T80T
tDDLTDeserializer Data Lock Time
See Figure 4-3.		Digital Reset, or PDB = HIGH to LOCK = HIGH10-bit mode22ms
12-bit HF mode22
12-bit LF mode22
tRCJReceiver Clock Jitter(1)PCLK, SSCG[0] = OFF10-bit mode4070ps
12-bit HF mode5290
12-bit LF mode4585
tDPJDeserializer Period Jitter(1)PCLK, SSCG[0] = OFF10-bit mode8851020ps
12-bit HF mode420880
12-bit LF mode400515
tDCCJDeserializer Cycle-to-Cycle Clock Jitter(1)(2)PCLK, SSCG[0] = OFF10-bit mode13601800ps
12-bit HF mode12801500
12-bit LF mode8901150
fdevSpread Spectrum Clocking Deviation Frequency
See Figure 4-9.		LVCMOS Output Bus, SSCG[0] = ON25 - 100 MHz±0.5% to ±2.5%
fmodSpread Spectrum Clocking Modulation Frequency
See Figure 4-9.		LVCMOS Output Bus, SSCG[0] = ON25 - 100 MHz5 to 50kHz
FPD-Link III
VINSingle Ended Input Voltage
See Figure 4-2.		Coaxial configuration. 1010 pattern applied to the far end of a 15 meter cable.
VIN measured after the cable, at the deserializer input pins.		50mV
VIDDifferential Input Voltage

See Figure 4-2.		STP Configuration. 1010 pattern applied to the far end of a 15 meter cable.
VID measured after the cable, at the deserializer input pins.		100mV
ƒBCBack Channel FrequencyRIN0+, RIN0–
RIN1+, RIN1–		3.55.5MHz
TJBack Channel Jitter(1)715ns
TIJITInput Jitter10MHz Sinusoidal Jitter applied to FPD-Link III input0.4UI(3)
(1) Specification is ensured by design and/or characterization and is not tested in production.
(2) Specification is ensured by characterization
(3) 1UI = 1 bit time of FPD-Link Forward channel