SLVSIL6C January   2026  – April 2026 INA151

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 INA151 Transconductance Architecture Overview
      2. 7.1.2 Multiplexing Capability
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Low Input Bias Current
      3. 7.3.3 Reference Voltage Range for G=1/4 (INA151D)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Enable and Disable
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Battery Monitoring Using INA151
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DC Accuracy Calculations
          2. 8.2.1.2.2 RC Filter Design Consideration
          3. 8.2.1.2.3 ADC Input Protection
        3. 8.2.1.3 Output Pullup Resistor in Multiplexer Configuration
        4. 8.2.1.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use the following PCB layout practices:

  • Verify that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals.
  • Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing in parallel with the noisy trace.
  • To minimize measurement errors, limit external series resistance (R1, R2) to 10 Ω or less. Higher resistance values cause higher voltage drop and can reduce measurement accuracy.
  • Place the external components as close to the device as possible.
  • Keep the traces as short as possible.