SLVSIL6C January   2026  – April 2026 INA151

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 INA151 Transconductance Architecture Overview
      2. 7.1.2 Multiplexing Capability
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Low Input Bias Current
      3. 7.3.3 Reference Voltage Range for G=1/4 (INA151D)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Enable and Disable
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Battery Monitoring Using INA151
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DC Accuracy Calculations
          2. 8.2.1.2.2 RC Filter Design Consideration
          3. 8.2.1.2.3 ADC Input Protection
        3. 8.2.1.3 Output Pullup Resistor in Multiplexer Configuration
        4. 8.2.1.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.1 DC Accuracy Calculations
Table 8-2 INA151B - Typical and Maximum DC Accuracy Calculations for FSR of 4.5V
Error Source Error Calculation for FSR=4.5V Spec
(Typ)		 Error
(PPM)		 Spec
(Max)		 Error
(PPM)
Absolute accuracy at 25°C of Cell1
Input stage offset voltage
VOSI		 V O S I F S R × 10 6 200μV 44.4 1200μV 266.7
Common-mode rejection ratio
CMRRERROR		 10 V C M C M R R 20 , V C M   =   0 V 140dB 0 125dB 0
Gain error from INA151
GE		 G E % × 10 6 0.01% 10 0.03 30
Total error (RSS) V O S I 2 + G E 2 + C M R R E R R O R 2 45.1 268.3
Absolute accuracy at 25°C of Cell16
Input stage offset voltage
VOSI		 V O S I F S R × 10 6 200μV 44.4 1200μV 268.3
Common-mode rejection ratio
CMRRERROR		 10 V C M C M R R 20 , V C M   =   67.5 V 140dB 1.5 125dB 37.9
Gain error from INA151
GE		 G E % × 10 6 0.01% 10 0.03% 30
Total error (RSS) V O S I 2 + G E 2 + C M R R E R R O R 2 45.5 272.6
Table 8-3 Typical Error Budget of C2000-xxF25 ADC
Error Source Parameter (typical) Voltage Error for CELL1 (ppm) Voltage Error for CELL16 (ppm)
ADC Offset Voltage 488 488
Gain Error 688 (at 3.1V) 688 (at 3.1V)
INL 244 244
ADC Typical Error 878 878
Total Typical Error (RSS) 902 902

Based on above error budget analysis the dominant error source is the internal ADC with a typical error value of 878ppm more then twenty larger compared to the error of INA151 with 45ppm. Considering RSS (Root-Sum-Squares) calculation of the errors results in a total error of 902ppm which relates to an accuracy of 0.09% of full scale.