SLVSIL6C January   2026  – April 2026 INA151

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 INA151 Transconductance Architecture Overview
      2. 7.1.2 Multiplexing Capability
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Low Input Bias Current
      3. 7.3.3 Reference Voltage Range for G=1/4 (INA151D)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Enable and Disable
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Battery Monitoring Using INA151
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DC Accuracy Calculations
          2. 8.2.1.2.2 RC Filter Design Consideration
          3. 8.2.1.2.3 ADC Input Protection
        3. 8.2.1.3 Output Pullup Resistor in Multiplexer Configuration
        4. 8.2.1.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from Revision B (March 2026) to Revision C (April 2026)

  • Changed Offset voltage from ±780μV to ±900μV in FeaturesGo
  • Added "common-mode" to paragraph "... and input impedance.." in DescriptionGo
  • Change Enable logic input voltage on EN pin from min. VDGND+0.3V to VDGNDGo
  • Add VDGND-VS/2 to Test ConditionsGo
  • Add line for differential-mode voltage with test condition of G=1/4 and TA=-40C to 125CGo
  • Change typical value of Enable input current from 1.3uA to 1.9uAGo
  • Changed internal node name where pull-up resistors of EN pin is connected from VS+ to VSub.Go
  • Changed from "VREF must stay at or below GND... for linear operating." to "Keep VREF at or below GND (down to negative supply, thus −5V) for linear operating including temperature and process variation." Go
  • Changed from "VREF must stay at or below 2V... for linear operating." to "Keep VREF at or below 2V (down to negative supply, thus −5V) for linear operating including temperature and process variation." Go
  • Changed Y-axis unit in Fig 7-6 from (V) to (μV).Go
  • Changed of 450μA to 430μA on the VS+ pin and −460μA on the VS− pin.Go
  • Changed of 300μA to ±300μAGo
  • Added pull-up resistor R1 in Fig 8-2.Go
  • Added section "Output Pullup Resistor in Multiplexer Configuration" with guidance on how to select R1Go
  • Added paragraph to Layout Guidelines "To minimize measurement errors, limit external series resistance (R1, R2) to 10Ω or less. Higher resistance values cause higher voltage drop and can reduce measurement accuracy."Go

Changes from Revision A (February 2026) to Revision B (March 2026)

  • Changed the device status from Advanced to Production dataGo

Changes from Revision * (January 2026) to Revision A (February 2026)

  • Change HBM value from 2kV to TBD in the ESD Ratings Go
  • Change CBM value from 1kV to TBD in the ESD Ratings Go