SLVSIL6C January   2026  – April 2026 INA151

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 INA151 Transconductance Architecture Overview
      2. 7.1.2 Multiplexing Capability
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Low Input Bias Current
      3. 7.3.3 Reference Voltage Range for G=1/4 (INA151D)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Enable and Disable
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Battery Monitoring Using INA151
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DC Accuracy Calculations
          2. 8.2.1.2.2 RC Filter Design Consideration
          3. 8.2.1.2.3 ADC Input Protection
        3. 8.2.1.3 Output Pullup Resistor in Multiplexer Configuration
        4. 8.2.1.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS = ±5 V, RL = 10 kΩ, VDGND = VREF = VCM = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage (RTI) VS = ±5V, VCM = 0V G=1 (A) ±0.3 ±0.9 mV
G=2/3 (B) ±0.37 ±1.3
G=1/2 (C) ±0.52 ±1.7
G=1/4 (D) ±0.96 ±3.4
Offset voltage drift (RTI)  TA = –40℃ to 125℃ G=1 (A) ±0.1 ±0.6 µV/°C
G=2/3 (B) ±0.15 ±0.92
G=1/2 (C) ±0.2 ±1.2
G=1/4 (D) ±0.4 ±2.4
PSRR Power-supply rejection ratio (RTI)  VS = ±1.35V to ±10V, VCM = (VS–) + 40V G=1 (A) 83 dB
G=2/3 (B) 79
G=1/2 (C) 76
G=1/4 (D) 69
VCM Common-mode voltage (1) TA = –40℃ to 125℃ (V–) + 4.3 (V–) + 110 V
VDM Differential-mode voltage (1) TA = –40℃ to 125℃ –5 5 V
TA = –40℃ to 125℃ G=1/4 –4.7 4.7
CMRR Common-mode voltage rejection VCM = –0.7V to 105V, RS = 0Ω G=1, 2/3, 1/2 125 137 dB
G=1/4 123 135
RVR Reference voltage rejection VREF = –4.7V to 4.7V G=1, 2/3 ±50 ±250 µV/V
VREF = –4.7V to 4.5V G=1/2 ±50 ±250
VREF = –4.7V to 0.1V G=1/4 ±50 ±250
Reverse input protection (V–) – 85 V
RDM Differential input impedance 45 kΩ
RCM Common-mode input impedance VCM = 0V to 110V 1 MΩ
Output impedance EN = HIGH See Typical Characteristics Ω
EN = LOW G=1 (A) 562.5 kΩ
G=2/3 (B) 395.83
G=1/2 (C) 312.5
G=1/4 (D) 187.5
IB Input bias current VDM = 0mV, IB+ 21 µA
VDM = 0mV, IB– 21
VDM = 5V, EN=HIGH(4) +55/–11
VDM = 5V, EN=LOW +/–30
Input bias current drift TA = –40℃ to 125℃ 1.8 nA/℃
IOS Input offset current(2) VDM= 0mV ±250 pA
Input offset current drift(2) TA = –40℃ to 125℃ 0.3 pA/℃
NOISE
eN Voltage noise (RTI) f = 1kHz G=1 (A) 485 nV/√Hz
G=2/3 (B) 502
G=1/2 (C) 506
G=1/4 (D) 576
GAIN
GE Gain error VDM = ±4.7V ±0.005 ±0.025 %
Gain error G=1/4 ±0.015 ±0.04
Gain error drift TA = –40°C to +125°C  0.05 2 ppm/°C
Gain non-linearity VDM= ±4.7V 2 ppm
OUTPUT
Output voltage RL = 10kΩ, TA = –40℃ to 125℃ (V–) + 0.3 (V+) – 0.3 V
CL Load capacitance Stable operation G=1 (A), 2/3 (B) 0.5 nF
G=1/2 (C), 1/4 (D) 0.3
ISC Short-circuit current Continuous to Vs/2 Sinking 25 mA
Sourcing 17
FREQUENCY RESPONSE
BW Bandwidth, –3 dB CL=100pF G=1 (A) 620 kHz
G=2/3 (B) 850
G=1/2 (C) 1080
G=1/4 (D) 1600
SR Slew rate VDM=±4.7V 2.2 V/µs
tS Settling time VDM= ±4.5V-step, VCM=5V G=1 (A) To 0.1% 9 µs
To 1% 4.8
G=2/3 (B) To 0.1% 7.6
To 1% 3.8
G=1/2 (C) To 0.1% 10.2
To 1% 2.7
G=1/4 (D) To 0.1% 8.9
To 1% 1.9
Output enable time To 0.1% 15 µs
Output disable time(3) To 0.1% 16
Overload recovery 50% input overload 16 µs
POWER SUPPLY
IQ(VS+) Quiescent current into VS+ VDM = 0V, EN = HIGH 430 550 µA
IQ(VS–) Quiescent current into VS– VDM = 0V, EN = HIGH –570 –460 µA
IQ Quiescent current into VS+/VS– VDM = 0V, EN = LOW ±300 µA
Quiescent current drift VDM = 0V, TA = –40℃ to 125℃ –0.07 µA/℃
ENABLE LOGIC
VEN Enable input logic low EN = LOW, DGND DGND DGND + 0.9 V
Enable input logic high EN = HIGH, DGND DGND + 2 DGND + 5 V
Enable input current VEN = DGND + 5V 1.9 µA
VDGND DGND voltage (VS+) – (VS–) ≤ 12.7V (VS–) (VS+) – 2.7 V
VDGND DGND voltage (VS+) – (VS–) > 12.7V (VS–) (VS–) + 10 V
(1) Keep both inputs above minimum requirement.
(2) Specified by design.
(3) Output disable time depends on the output network of the device which is different for each variant and the load connected. See Typical Characteristics for more information.
(4) Asymmetrical input bias current flow, positive IB flowing into the device, negative IB flowing out of the device. See chapter "Low Input Bias Current" for more information.