SBOS776C March   2016  – March 2021 INA3221-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Basic ADC Functions
      2. 8.3.2 Alert Monitoring
        1. 8.3.2.1 Critical Alert
          1. 8.3.2.1.1 Summation Control Function
        2. 8.3.2.2 Warning Alert
        3. 8.3.2.3 Power-Valid Alert
        4. 8.3.2.4 Timing-Control Alert
        5. 8.3.2.5 Default Settings
      3. 8.3.3 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Averaging Function
      2. 8.4.2 Multiple Channel Monitoring
        1. 8.4.2.1 Channel Configuration
        2. 8.4.2.2 Averaging and Conversion-Time Considerations
      3. 8.4.3 Filtering and Input Considerations
    5. 8.5 Programming
      1. 8.5.1 Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing To and Reading From the INA3221-Q1
        1. 8.5.2.1 High-Speed I2C Mode
      3. 8.5.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Register Set
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1  Configuration Register (address = 00h) [reset = 7127h]
        2. 8.6.2.2  Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
        3. 8.6.2.3  Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
        4. 8.6.2.4  Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
        5. 8.6.2.5  Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
        6. 8.6.2.6  Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
        7. 8.6.2.7  Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
        8. 8.6.2.8  Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
        9. 8.6.2.9  Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
        10. 8.6.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
        11. 8.6.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
        12. 8.6.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
        13. 8.6.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
        14. 8.6.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
        15. 8.6.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
        16. 8.6.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
        17. 8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
        18. 8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
        19. 8.6.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
        20. 8.6.2.20 Die ID Register (address = FFh) [reset = 3220]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 Design Requirements

For this design example, use the input parameters shown in Table 9-1. All other register settings are default.

Table 9-1 Design Parameters
DESIGN PARAMETEREXAMPLE VALUE
Supply voltage, VS5 V
Pull-up resistors10 kΩ
Input range–163.84 to +163.8
Enabled channelCH1
Operating modeShunt voltage, continuous
Average setting1
Critical alert limit80 mV
Critical Alert Limit register setting7D0h