To access a specific INA3221-Q1 register, write the appropriate value to the register pointer. See Table 8-3 for a complete list of registers and corresponding addresses. The value for the register pointer, as shown in Figure 8-9, is the first byte transferred after the slave address byte with the R/ W bit low. Every write operation to the INA3221-Q1 requires a register pointer value.

The value of the Slave Address Byte is determined by the A0 pin setting; see Table 8-1.

Figure 8-9 Typical Register Pointer Set

Register writes begin with the first byte transmitted by the master. This byte is the slave address, with the R/ W bit low. The INA3221-Q1 then acknowledges receipt of a valid address. The next byte transmitted by the master is the register address that data are written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA3221-Q1 acknowledges receipt of each data byte. The master terminates data transfer by generating a start or stop condition.

When reading from the INA3221-Q1, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, write a new value to the register pointer. This write is accomplished by issuing a slave address byte with the R/ W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master terminates data transfer by generating a not-acknowledge after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA3221-Q1 retains the register pointer value until it is changed by the next write operation.

Figure 8-10 and Figure 8-11 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

The value of the slave address byte is determined by the A0 pin setting; see Table 8-1.

Figure 8-10 Timing Diagram for Write Word Format

The value of the slave address byte is determined by the A0 pin setting; see Table 8-1.

Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 8-9.

The master can also send an ACK.

Figure 8-11 Timing Diagram for Read Word Format

Figure 8-12 shows the timing diagram for the SMBus Alert response operation.

The value of the Slave Address Byte is determined by the A0 pin setting; see Table 8-1.

Figure 8-12 Timing Diagram for SMBus Alert