SBOSAI8A March   2025  – July 2025 INA630

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Gain
        1. 7.3.1.1 Gain Error and Drift
      2. 7.3.2 Linear Input Voltage Range
      3. 7.3.3 Input Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reference Pin
      2. 8.1.2 Input Bias Current Return Path
    2. 8.2 Typical Applications
      1. 8.2.1 Current Shunt Monitoring in Battery Testing Systems
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 10kΩ, VREF = 0V, and G = 20 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (INP, INN)
VOS Offset voltage RTI –60 ±350 µV
RTI, TA = –40°C to +125°C ±450
Offset voltage drift(1) RTI, TA = –40°C to +125°C ±0.7 ±2 µV/°C
PSRR Power-supply rejection ratio RTI, VS = ±2.25V to ±18V 123 130 dB
CMRR Common-mode rejection ratio At DC to 60Hz, RTI
VCM = (V–) + 1.75V to (V+) – 1.5V
G = 20 to 1000		 126 133 dB
INPUT (INP, INN, VREF, VFB)
zid Differential impedance 100 || 1 GΩ || pF
zic Common-mode impedance 100 || 7 GΩ || pF
VCM Operating voltage VS = ±2.25V to ±18V, TA = –40°C to +125°C (V–) + 1.75 (V+) – 1.5 V
VDM Differential operating voltage VS = ±2.25V to ±18V, TA = –40°C to +125°C –125 125 mV
IB Input bias current(2) VCM = VS/2 2.5 15 nA
Input bias current drift(1) TA = –40°C to +125°C 15 pA/℃
IOS Input offset current VCM = VS/2 9 250 pA
Input offset current drift(1) TA = –40°C to +125°C 1.5 pA/℃
NOISE VOLTAGE
eN Voltage noise f = 1kHz, G = 20, 100, RS = 0Ω 36 nV/√Hz
EN fB = 0.1Hz to 10Hz, G = 20 or 100, RS = 0Ω 0.9 µVPP
iN Current noise f = 1kHz 40 fA/√Hz
fB = 0.1Hz to 10Hz, G = 100 3 pAPP
GAIN
G Gain equation 1+R2 / R1 V/V
Gain range 20 1000 V/V
GE Gain error(1) R1 = 1kΩ G = 20, VO = ±2.5V ±0.03 0.15 %
G = 100, VO = ±10V ±0.05 0.15
Gain drift(1) TA = –40°C to +125°C G = 20 3 10 ppm/°C
G = 100 2.5 8 ppm/°C
Gain nonlinearity(1) , RL = 10kΩ G = 20, VO = –2.5V to 2.5V 40 ppm
G = 100, VO = –10V to 10V 1 10 ppm
OUTPUT
Output voltage swing (V–) + 1.75 (V+) – 1.5 V
Load capacitance stability 1000 pF
ZO Closed-loop output impedance f = 10kHz 100 Ω
ISC Short-circuit current Continuous to VS/2 ±20 mA
FREQUENCY RESPONSE
BW Bandwidth, –3dB G = 20 550 kHz
G = 100 100
G = 1000 10
SR Slew rate G = 20, VO = ±2.5V 3.5 V/µs
G = 100, VO = ±2.5V 1.5
tS Settling time 0.01%, VSTEP = 5V G = 20 5 µs
G = 100 15
0.001%, VSTEP = 5V G = 20 7.5
G = 100 25
POWER SUPPLY
IQ Quiescent current VIN = 0V 300 375 µA
vs temperature, TA = –40°C to +125°C 475
(1) Specified by design and characterization.
(2) The input stage has NPN transistors, thus the input bias current flows into the device.