SLLS897F march   2008  – august 2023 ISO1176

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics: Driver
    10. 6.10 Electrical Characteristics: Receiver
    11. 6.11 Supply Current
    12. 6.12 Electrical Characteristics: ISODE-Pin
    13. 6.13 Switching Characteristics: Driver
    14. 6.14 Switching Characteristics: Receiver
    15. 6.15 Insulation Characteristics Curves
    16. 6.16 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transient Voltages
        2. 9.2.2.2 ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-549F8B2C-1A19-45CD-AAD3-67648E945A10-low.gif Figure 5-1 DW Package
16-Pin SOIC
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A 12 I/O Noninverting bus output
B 13 I/O Inverting bus output
D 6 I Driver input
DE 5 I Driver logic-high enable
GND1 2, 8 — Logic-side ground; internally connected
GND2 9, 15 — Bus-side ground; internally connected
ISODE 10 — Bus-side driver enable output
NC 11, 14 — Not connected internally; may be left floating
PV 7 I ISO1176 chip enable, logic high applied immediately after power up for device operation.
A logic low 3-states all outputs.
R 3 O Receiver output
RE 4 I Receiver logic-low enable
VCC1 1 — Logic side power supply
VCC2 16 — Bus side power supply