SLLS897E March   2008  – June 2015 ISO1176

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ISODE-Pin
    6. 7.6  Supply Current
    7. 7.7  Electrical Characteristics: Driver
    8. 7.8  Electrical Characteristics: Receiver
    9. 7.9  Power Dissipation Characteristics
    10. 7.10 Switching Characteristics: Driver
    11. 7.11 Switching Characteristics: Receiver
    12. 7.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Insulation and Safety-Related Package Characteristics
      2. 9.3.2 DIN V VDE V 0884-10 Insulation Characteristics
      3. 9.3.3 IEC 60664-1 Ratings Table
      4. 9.3.4 Safety Limiting Values
      5. 9.3.5 Regulatory Information
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Transient Voltages
        2. 10.2.2.2 ISO1176 “Sticky Bit” Issue (Under Certain Conditions)
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The ISO1176 is an isolated half-duplex differential line transceiver that meets the requirements of EN 50170 and TIA/EIA 485/422 applications. The device is rated to provide galvanic isolation of up to 2500 VRMS for 60 s per UL 1577. The device has active-high driver enable and active-low receiver enable functions to control the data flow. The device has maximum data transmission speed of 40 Mbps.

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = V(A) – V(B) is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT– , the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

9.2 Functional Block Diagram

ISO1176 fbd1_slls897.gif

9.3 Feature Description

9.3.1 Insulation and Safety-Related Package Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm
L(I02) Minimum external tracking (Creepage)(1) Shortest terminal-to-terminal distance across the package surface 8.1 mm
CTI Tracking resistance (Comparative Tracking Index) DIN IEC 60112 / VDE 0303 Part 1 ≥400 V
Minimum internal gap (Internal Clearance) Distance through the insulation 0.008 mm
RIO Isolation resistance Input to output, VIO = 500 V, TA = 25°C, all pins on each side of the barrier tied together creating a 2-terminal device >1012 Ω
CIO Barrier capacitance Input to output VI = 0.4 sin (4E6πt) 2 pF
CI Input capacitance to ground VI = 0.4 sin (4E6πt) 2 pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit-board (PCB) do not reduce this distance.
Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a PCB are used to help increase these specifications.

9.3.2 DIN V VDE V 0884-10 Insulation Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIOTM Transient overvoltage t = 60 s 4000 VPK
VIORM Maximum working insulation voltage 560 VPK
VPR Input to output test voltage Method b1, VPR = VIORM × 1.875, 100% Production test with t = 1 s, Partial discharge <5 pC 1050 VPK
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2

9.3.3 IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Installation classification Rated mains voltage < 150 VRMS I-IV
Rated mains voltage < 300 VRMS I-III

9.3.4 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current-limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current DW-16 RθJA = 168°C/W, VI = 5.5 V, TJ = 170°C,
TA = 25°C
157 mA
TS Maximum case temperature DW-16 150 °C

The safety-limiting constraint is the absolute maximum junction temperature specified in Absolute Maximum Ratings. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in Thermal Information is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative.

The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance..

ISO1176 D001_SLLS897.gifFigure 28. DW-16 RθJC Thermal Derating Curve per VDE

9.3.5 Regulatory Information

VDE CSA UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Approved under CSA Component Acceptance Notice 5A and IEC 60950-1 Recognized under UL 1577 Component Recognition Program(1)
Basic insulation,
4000 VPK Maximum transient overvoltage,
560 VPK Maximum working voltage
4000 VPK Isolation rating,
560 VPK Basic working voltage per CSA 60950-1-07 and IEC 60950-1 (2nd Ed)
Single Protection, 2500 VRMS
Certificate number: 40016131 Master contract number: 220991 File number: E181974
(1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.

9.4 Device Functional Modes

Table 1. Driver Function Table(1)

VCC1 VCC2 POWER VALID
(PV) (ISO1176)
INPUT
(D)
ENABLE INPUT
(DE)
ENABLE OUTPUT (ISODE) OUTPUTS
A B
PU PU H or open H H H H L
PU PU H or open L H H L H
PU PU H or open X L L Z Z
PU PU H or open X open L Z Z
PU PU H or open open H H H L
PD PU X X X L Z Z
PU PD X X X L Z Z
PD PD X X X L Z Z
X X L X X L Z Z
(1) PU = powered up, PD = powered down, H = high level, L= low level, X = don’t care, Z = high impedance (off)

Table 2. Receiver Function Table(1)

VCC1 VCC2 POWER VALID
(PV) (ISO1176)
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
PU PU H or open –0.01 V ≤ VID L H
PU PU H or open –0.2 V < VID < –0.01 V L ?
PU PU H or open VID ≤ –0.2 V L L
PU PU H or open X H Z
PU PU H or open X open Z
PU PU H or open Open-circuit L H
PU PU H or open Short-circuit L H
PU PU H or open Idle (terminated) bus L H
PD PU X X X Z
PU PD H or open X L H
PD PD X X X Z
X X L X X Z
(1) PU = powered up, PD = powered down, H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
ISO1176 eq_sch_lls897.gifFigure 29. Equivalent I/O Schematics
ISO1176 eq2_sch_lls897.gifFigure 30. Equivalent I/O Schematics for A and B Inputs and Outputs