SLLSF22H April 2018 – June 2024 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 6-1 DW Package16-Pin SOICFull-Duplex Device Top View| PIN | Type(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A | 14 | I | Receiver non-inverting input on the bus side |
| B | 13 | I | Receiver inverting input on the bus side |
| D | 6 | I | Driver input |
| DE | 5 | I | Driver enable. This pin enables the driver output when high and disables the driver output when low or open. |
| GND1(2) | 2 | — | Ground connection for VCC1 |
| GND1(2) | 8 | — | Ground connection for VCC1 |
| GND2(2) | 9 | — | Ground connection for VCC2 |
| GND2(2) | 15 | — | Ground connection for VCC2 |
| NC(3) | 7 | — | No internal connection |
| NC(3) | 10 | — | No internal connection |
| R | 3 | O | Receiver output |
| RE | 4 | I | Receiver enable. This pin disables the receiver output when high or open and enables the receiver output when low. |
| VCC1 | 1 | — | Logic-side power supply |
| VCC2 | 16 | — | Transceiver-side power supply |
| Y | 11 | O | Driver non-inverting output |
| Z | 12 | O | Driver inverting output |