SWRS228A September 2019 – January 2022 IWR1843
The supported IWR1843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The LVDS interface supports the following data rates:
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.