SWRS228A September 2019 – January 2022 IWR1843
The IWR1843 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device pins. Figure 8-3 shows the crystal implementation.
The load capacitors, Cf1 and Cf2 in Figure 8-3, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins.
Table 8-5 lists the electrical characteristics of the clock crystal.
|fP||Parallel resonance crystal frequency||40||MHz|
|CL||Crystal load capacitance||5||8||12||pF|
|Temperature range||Expected temperature range of operation||–40||105||°C|
|Frequency tolerance||Crystal frequency tolerance(1)(2)||–200||200||ppm|
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-6 lists the electrical characteristics of the external clock signal.
External AC-coupled sine wave or DC-coupled square wave
Phase Noise referred to 40 MHz
|Phase Noise at 1 kHz||–132||dBc/Hz|
|Phase Noise at 10 kHz||–143||dBc/Hz|
|Phase Noise at 100 kHz||–152||dBc/Hz|
|Phase Noise at 1 MHz||–153||dBc/Hz|