SNVSB28 December   2017 LM25575-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage Start-Up Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown and Stand-by Mode
      2. 7.4.2 Error Amplifier and PWM Comparator
      3. 7.4.3 Ramp Generator
      4. 7.4.4 Maximum Duty Cycle and Input Drop-out Voltage
      5. 7.4.5 Current Limit
      6. 7.4.6 Soft-Start
      7. 7.4.7 Boost Pin
      8. 7.4.8 Thermal Protection
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  External Components
      2. 8.1.2  R3 (RT)
      3. 8.1.3  L1
      4. 8.1.4  C3 (CRAMP)
      5. 8.1.5  C9, C10
      6. 8.1.6  D1
      7. 8.1.7  C1, C2
      8. 8.1.8  C8
      9. 8.1.9  C7
      10. 8.1.10 C4
      11. 8.1.11 R5, R6
      12. 8.1.12 R1, R2, C12
      13. 8.1.13 R7, C11
      14. 8.1.14 R4, C5, C6
      15. 8.1.15 BIas Power Dissipation Reduction
    2. 8.2 Typical Application
      1. 8.2.1 Typical Schematic for High Frequency (1 MHz) Application
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Layout and Thermal Considerations
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Developmental Support
        1. Custom Design With WEBENCH® Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

PCB Layout and Thermal Considerations

The circuit in Functional Block Diagram serves as both a block diagram of the LM25575-Q1 and a typical application board schematic for the LM25575-Q1. In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitors, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the regulator IS pins, to the diode anode, to the inductor and then out to the load. Minimizing the loop area of these two loops reduces the stray inductance and minimizes noise and possible erratic operation. A ground plane in the PC board is recommended as a means to connect the input filter capacitors to the output filter capacitors and the PGND pins of the regulator. Connect all of the low power ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND and PGND pins together through the topside copper area covering the entire underside of the device. Place several vias in this underside copper area to the ground plane.

The two highest power dissipating components are the re-circulating diode and the LM25575-Q1 regulator IC. The easiest method to determine the power dissipated within the LM25575-Q1 is to measure the total conversion losses (Pin – Pout) then subtract the power losses in the Schottky diode, output inductor and snubber resistor. An approximation for the Schottky diode loss is P = (1-D) × Iout × Vfwd. An approximation for the output inductor power is P = IOUT2 × R × 1.1, where R is the DC resistance of the inductor and the 1.1 factor is an approximation for the AC losses. If a snubber is used, an approximation for the damping resistor power dissipation is P = VIN2 × Fsw × Csnub, where Fsw is the switching frequency and Csnub is the snubber capacitor. The regulator has an exposed thermal pad to aid power dissipation. Adding several vias under the device to the ground plane will greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will aid the power dissipation of the diode.

The most significant variables that affect the power dissipated by the LM25575-Q1 are the output current, input voltage and operating frequency. The power dissipated while operating near the maximum output current and maximum input voltage can be appreciable. The operating frequency of the LM25575-Q1 evaluation board has been designed for 300 kHz. When operating at 1.5 A output current with a 42 V input the power dissipation of the LM25575-Q1 regulator is approximately 0.9 W.

The junction-to-ambient thermal resistance of the LM25575-Q1 will vary with the application. The most significant variables are the area of copper in the PC board, the number of vias under the IC exposed pad and the amount of forced air cooling provided. Referring to the evaluation board artwork, the area under the LM25575-Q1 (component side) is covered with copper and there are 5 connection vias to the solder side ground plane. Additional vias under the IC will have diminishing value as more vias are added. The integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal dissipation capacity. The junction-to-ambient thermal resistance of the LM25575-Q1 mounted in the evaluation board varies from 50°C/W with no airflow to 28°C/W with 900 LFM (Linear Feet per Minute). With a 25°C ambient temperature and no airflow, the predicted junction temperature for the LM25575-Q1 will be 25 + (50 × 0.9) = 70°C. If the evaluation board is operated at 1.5 A output current, 70 V input voltage and high ambient temperature for a prolonged period of time the thermal shutdown protection within the IC may activate. The IC will turn off allowing the junction to cool, followed by restart with the soft-start capacitor reset to zero.

Table 1. 5 V, 1.5 A Demo Board Bill of Materials

C 1 C3225X7R2A105M CAPACITOR, CER, TDK 1 µ, 100 V
C 2 C3225X7R2A105M CAPACITOR, CER, TDK 1 µ, 100 V
C 3 C0805A471K1GAC CAPACITOR, CER, KEMET 470 p, 100 V
C 4 C2012X7R2A103K CAPACITOR, CER, TDK 0.01 µ, 100 V
C 5 C2012X7R2A103K CAPACITOR, CER, TDK 0.01 µ, 100 V
C 7 C2012X7R2A223K CAPACITOR, CER, TDK 0.022 µ, 100 V
C 8 C2012X7R1C474M CAPACITOR, CER, TDK 0.47 µ, 16 V
C 9 C3225X7R1C106M CAPACITOR, CER, TDK 10 µ, 16 V
C 11 C0805C331G1GAC CAPACITOR, CER, KEMET 330 p, 100 V
L 1 DR125-470 INDUCTOR, COOPER 47 µH
R 3 CRCW08052102F RESISTOR 21 kΩ
R 4 CRCW08054992F RESISTOR 49.9 kΩ
R 5 CRCW08055111F RESISTOR 5.11 kΩ
R 6 CRCW08051651F RESISTOR 1.65 kΩ
R 7 CRCW2512100J RESISTOR 10, 1 W