SNVS961F April   2013  – October 2026 LM5023

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Detailed Pin Description
        1. 6.3.1.1 QR Pin
        2. 6.3.1.2 VSD Pin
        3. 6.3.1.3 SS Pin
        4. 6.3.1.4 COMP Pin
        5. 6.3.1.5 CS Pin
        6. 6.3.1.6 GND Pin
        7. 6.3.1.7 OUT Pin
        8. 6.3.1.8 VCC Pin
      2. 6.3.2 Start-Up
      3. 6.3.3 Quasi-Resonant Operation
      4. 6.3.4 Quasi-Resonant Operating Frequency
      5. 6.3.5 PWM Comparator
      6. 6.3.6 Soft-Start
      7. 6.3.7 Gate Driver
        1. 6.3.7.1 Skip-Cycle Operation
      8. 6.3.8 Current Limit and Current Sense
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Line Current-Limit Feedforward
          1. 7.2.2.2.1 Overvoltage Protection
        3. 7.2.2.3 Valley Switching
        4. 7.2.2.4 Hiccup Mode
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Start-Up

Referring to Figure 6-1, when the AC rectified line voltage is applied to the bulk-energy-storage capacitor; the N-channel depletion mode MOSFET is turned on and supplies the charging current to the VCC capacitor. When the voltage on the VCC pin reaches 12.5V typical, the PWM controller, soft-start circuit and gate driver are enabled.

When the LM5023 is enabled and the OUT drive signal starts switching the flyback MOSFET, energy is being stored and then transferred from the transformer primary to the secondary windings. A bias winding, shown in Figure 6-1, delivers energy to the VCC capacitor to sustain the voltage on the VCC pin. The voltage supplied from the auxiliary winding must be within the range from 10V to 14V (where 16V is the absolute maximum rating).

After reaching the VCCON threshold, the LM5023 VSD open-drain output, which is pulled up to VCC during start up, goes low. This applies a negative gate to source voltage on the depletion mode MOSFET turning it off. This disables the high-voltage start-up circuit. The high-voltage start-up circuit can be implemented in either of two ways; the first is shown in Figure 6-1, which uses an N-channel depletion mode FET, the second is shown in Figure 6-2, which uses an N-channel enhancement mode FET. The circuit using the depletion mode FET has the lowest standby power. The standby power consumption of the FET is the voltage across the start-up FET multiplied by the drain-to-source cutoff current with gate negatively biased, this is typically 0.1µA.

Standby power of the start-up FET calculation is shown in Equation 1 through Equation 5.

Equation 1. VIN=230VAC
Equation 2. VCC=10V
Equation 3. VDC(max)=230VAC×2=325VDC
Equation 4. ID(off)=0.1μA

where

  • ID(off) is the depletion mode FETs leakage current
Equation 5. Pd=ID(off)×VDC(max)=0.1μA×325VDC=32.5μW

When VCC < VCCON the standby current consumption of the IC = ICC(st), nominally 340µA.

LM5023 Start-Up With a Depletion Mode FETFigure 6-1 Start-Up With a Depletion Mode FET

An alternative start-up circuit employs an enhancement mode FET with pull-up resistors connected from the rectified DC bus to the gate of the FET, Figure 6-2. After the input AC power is applied, the enhancement mode FET supplies the charging current to the VCC capacitor CVCC. After reaching the VCCON threshold, the LM5023 VSD open-drain output, which is pulled up to VCC during start up, goes low. This grounds the gate of the start-up MOSFET, turning it off. The start-up resistors are always in the circuit, therefore the standby power consumed is higher than if using a depletion mode FET.

Equation 6. VIN=230VAC
Equation 7. VCC=10V
Equation 8. VDC(max)=230VAC×2=325VDC
Equation 9. R START-UP = 10 MΩ
Equation 10. P RESISTORS = V DC 2 R START-UP = 325 2 10 M Ω = 10 . 56 mW
LM5023 Start-Up With an Enhancement Mode FETFigure 6-2 Start-Up With an Enhancement Mode FET