SLVSFF1C December   2021  – November 2025 LM5123-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Enable/Disable (EN, VH Pin)
      2. 7.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 7.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 7.3.4  VOUT Range Selection (RANGE Pin)
      5. 7.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 7.3.6  Fast Restart Using VCC HOLD (VH Pin)
      7. 7.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 7.3.8  Overvoltage Protection (VOUT Pin)
      9. 7.3.9  Power Good Indicator (PGOOD Pin)
      10. 7.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 7.3.11 External Clock Synchronization (SYNC Pin)
      12. 7.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 7.3.13 Programmable Soft Start (SS Pin)
      14. 7.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 7.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 7.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 7.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      18. 7.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      19. 7.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      20. 7.3.20 Thermal Shutdown Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Status
        1. 7.4.1.1 Shutdown Mode
        2. 7.4.1.2 Configuration Mode
        3. 7.4.1.3 Active Mode
        4. 7.4.1.4 Sleep Mode
        5. 7.4.1.5 Deep Sleep Mode
      2. 7.4.2 Light Load Switching Mode
        1. 7.4.2.1 Forced PWM (FPWM) Mode
        2. 7.4.2.2 Diode Emulation (DE) Mode
        3. 7.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 7.4.2.4 Skip Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Ideas
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGR|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values correspond to TJ = 25 °C. Minimum and maximum limits apply over TJ = -40 °C to 125 °C. Unless otherwise stated, VBIAS = 12V, VVOUT = 12V, RT = 9.09kΩ, , RVREF = 65kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT(BIAS, VCC, VOUT)
IBIAS-SD BIAS current in shutdown VUVLO = 0V, VOUT = 11.3V 2.5 5 µA
IBIAS-DS1 BIAS current in deep sleep (Skip or Diode emulation mode, Charge pump off, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 0V, VOUT = 12V 10 16 µA
IBIAS-DS2 BIAS current in deep sleep (FPWM mode, Charge pump off, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 0V, VOUT = 12V 40 69 µA
IBIAS-DS3 BIAS current in deep sleep (Skip or Diode emulation mode, Charge pump on, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 2.5V, VOUT = 12V 32 60 µA
IBIAS-DS4 BIAS current in deep sleep (FPWM mode, Charge pump on, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 2.5V, VOUT = 12V 114 154 µA
IBIAS-SLEEP BIAS current in sleep (Skip mode, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.25V, MODE = OPEN, VOUT = 5V 13 17.5 µA
IBIAS-ACTIVE BIAS current in active (Non-switching, VCC is supplied by BIAS) VUVLO = 2.5V, VTRK = 0.6V, MODE = VCC 1.2 1.5 mA
IVOUT-SD VOUT current in shutdown VUVLO = 0V, VOUT = 11.3V 1 µA
IVOUT-DS VOUT current in deep sleep (Diode emulation mode) VUVLO = 2.5V, VTRK = 0.25V, VOUT = 12V 1.2 1.5 µA
IVOUT-ACTIVE VOUT current in active (Non-switching) VUVLO = 2.5V, VTRK = 0.6V, MODE = VCC 42 55 µA
IBATTERY-SD Battery drain in shutdown VUVLO = 0V, VOUT = 11.3V 2.5 5 µA
IBATTERY-DS1 Battery drain in deep sleep (Skip or Diode emulation mode, Charge pump off) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 0V 11 17 µA
IBATTERY-DS2 Battery drain in deep sleep (FPWM mode, Charge pump off) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 0V 41 70 µA
IBATTERY-DS3 Battery drain in deep sleep (Skip or Diode Emulation mode, Charge pump on) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 2.5V 33 62 µA
IBATTERY-DS4 Battery drain in deep sleep (FPWM mode, Charge pump on) VUVLO = 2.5V, VTRK = 0.25V, VSYNC = 2.5V 115 155 µA
ENABLE, UVLO
VEN-RISING Enable threshold EN rising 0.45 0.55 0.65 V
VEN-FALLING Enable threshold EN falling 0.35 0.45 0.55 V
VEN-HYS Enable hysteresis EN falling 55 90 130 mV
IUVLO-HYS UVLO pull-down hysteresis current VUVLO = 0.7V 8 10 12 µA
VUVLO-RISING UVLO threshold UVLO rising 1.05 1.1 1.15 V
VUVLO-FALLING UVLO threshold UVLO falling 1.025 1.075 1.125 V
VUVLO-HYS UVLO hysteresis UVLO falling 25 mV
SYNC/DITHER/VH/CP
VSYNC-RISING SYNC threshold/SYNC detection threshold SYNC rising 2 V
VSYNC-FALLING SYNC threshold SYNC falling 0.4 V
Minimum SYNC pull up pulse width 100 ns
IDITHER Dither source/sink current 16 21 26 µA
ΔfSW1 fSW Modulation (Upper Limit) 5 %
ΔfSW2 fSW Modulation (Lower Limit) –6 %
VDITHER-FALLING Dither disable threshold 0.65 0.75 0.85 V
VCC
VVCC-REG1 VCC regulation IVCC = 100mA 4.75 5 5.25 V
VVCC-REG2 VCC regulation No load 4.75 5 5.25 V
VVCC-REG3 VCC regulation during dropout VBIAS = 3.8V, IVCC = 100mA 3.45 V
VVCC-UVLO-RISING VCC UVLO threshold VCC rising 3.55 3.65 3.75 V
VVCC-UVLO-FALLING VCC UVLO threshold VCC falling 3.2 3.3 3.4 V
IVCC-CL VCC sourcing current limit VVCC = 4V 100 mA
CONFIGURATION (MODE)
VMODE-RISING FPWM mode threshold MODE rising 2.0 V
VMODE-FALLING Diode emulation mode threshold MODE falling 0.4 V
RT
VRT RT regulation 0.5 V
VREF, TRK, VOUT
VREF VREF regulation target 0.99 1 1.005 V
VOUT-REG VOUT regulation target1 with resistor divider (Lower VOUT range) VREF resistor divider to make VTRK = 0.25V, RVREF = 65kΩ 4.915 5 5.085 V
VOUT-REG VOUT regulation target2 with resistor divider (Lower VOUT range) VREF resistor divider to make VTRK = 0.5V, RVREF = 65kΩ 9.9 10 10.1 V
VOUT-REG VOUT regulation target3 with resistor divider (Lower VOUT range) VREF resistor divider to make VTRK = 1.0V, RVREF = 65kΩ 19.8 20 20.2 V
VOUT-REG VOUT regulation target4 with resistor divider (Upper VOUT range) VREF resistor divider to make VTRK = 0.25V, RVREF = 35kΩ 14.74 15 15.24 V
VOUT-REG VOUT regulation target5 with resistor divider (Upper VOUT range) VREF resistor divider to make VTRK = 0.5V, RVREF = 35kΩ 29.7 30 30.3 V
VOUT-REG VOUT regulation target6 with resistor divider (Upper VOUT range) VREF resistor divider to make VTRK = 0.95V, RVREF = 35kΩ 56.43 57 57.57 V
VOUT-REG VOUT regulation target1 using TRK (Lower VOUT range) VTRK = 0.25V, RVREF = 65kΩ 4.91 5 5.09 V
VOUT-REG VOUT regulation target2 using TRK (Lower VOUT range) VTRK = 0.5V, RVREF = 65kΩ 9.88 10 10.11 V
VOUT-REG VOUT regulation target3 using TRK (Lower VOUT range) VTRK = 1.0V, RVREF = 65kΩ 19.8 20 20.2 V
VOUT-REG VOUT regulation target4 using TRK (Upper VOUT range) VTRK = 0.25V, RVREF = 35kΩ 14.71 15 15.25 V
VOUT-REG VOUT regulation target5 using TRK (Upper VOUT range) VTRK = 0.5V, RVREF = 35kΩ 29.6 30 30.3 V
VOUT-REG VOUT regulation target6 using TRK (Upper VOUT range) VTRK = 0.95V, RVREF = 35kΩ 56.45 57 57.5 V
ITRK TRK bias current 1 uA
SOFT START, DE to FPWM TRANSITION
ISS Soft-start current 17 20 23 µA
VSS-DONE MODE transition start SS rising 1.3 1.5 1.7 V
RSS SS pull-down switch RDSON 30 70 Ω
VSS-DIS SS discharge detection threshold 30 50 75 mV
VSS-FB internal SS to FB clamp VFB=0V 55 75 mV
CURRENT SENSE (CSP, CSN, SW, SENSE)
VSLOPE Peak slope compensation amplitude Referenced to CS input 45 mV
ACS Current sense amplifier gain CSP=3.0V 10 V/V
Current sense amplifier gain CSP=1.5V 10 V/V
VCLTH Positive peak current limit threshold (CSP-CSN) CSP=3.0V, MODE = GND 54 60 66 mV
Positive peak current limit threshold (CSP-CSN) CSP=1.5V, MODE = GND 51 60 72 mV
VZCD-DE ZCD threshold (SW-SENSE) MODE = GND 4 mV
ICSN CSN bias current 1 µA
ICSP CSP bias current 110 µA
BOOT FAULT PROTECTION (HB)
Maximum replenish pulse cycles 4 cycles
Replenish off cycles 12 cycles
Number of sets to enter hiccup mode protection 4 sets
Off-cycle during hiccup mode off 512 cycles
ERROR AMPLIFIER (COMP)
Gm Transconductance 1 mA/V
ISOURCE-MAX Maximum COMP sourcing current VCOMP=0V 95 µA
ISINK-MAX Maximum COMP sinking current VCOMP=1.8V 90 µA
VCLAMP-MAX COMP maximum clamp voltage COMP rising 1.8 2.2 2.55 V
VCLAMP-MIN COMP minimum clamp voltage, active in sleep and deep sleep mode. COMP falling 0.25 V
PULSE WIDTH MODULATION (PWM)
fSW1 Switching frequency RT = 220kΩ 85 100 115 kHz
fSW2 Switching frequency RT = 9.09kΩ 1980 2200 2420 kHz
tON-MIN Minimum controllable on-time RT = 9.09kΩ 14 20 50 ns
tOFF-MIN Minimum forced off-time RT = 9.09kΩ 70 95 115 ns
DMAX1 Maximum duty cycle limit  RT = 220kΩ 90 94 98 %
DMAX2 Maximum duty cycle limit  RT = 9.09kΩ 75 80 83 %
LOW IQ SLEEP MODE
VWAKE Internal wakeup threshold VOUT falling (referenced to VOUT-REG) 98.5 %
Sleep to Wake-up delay RT = 9.09kΩ 5 us
PGOOD, OVP
VOVTH-RISING Overvoltage threshold (OVP threshold) VOUT rising (referece to VOUT-REG) 104.5 108 111 %
VOVTH-FALLING Overvoltage threshold (OVP threshold) VOUT falling (referece to VOUT-REG) 100.5 105 109 %
VUVTH-RISING Undervoltage threshold (PGOOD threshold) VOUT rising (referece to VOUT-REG) 91.5 94 98 %
VUVTH-FALLING Undervoltage threshold (PGOOD threshold) VOUT falling (referece to VOUT-REG) 89.5 92 95.5 %
UV comparator deglich filter Rising edge 26 µs
UV comparator deglich filter Falling edge 21 µs
RPGOOD PGOOD pull-down switch RDSON 90 180 Ω
Minimum BIAS for valid PGOOD 2.5 V
MOSFET DRIVER
High-state voltage drop (HO driver) 100mA sinking 0.08 0.15 V
Low-state voltage drop (HO driver) 100mA sourcing 0.04 0.1 V
High-state voltage drop (LO driver) 100mA sinking 0.08 0.17 V
Low-state voltage drop (LO driver) 100mA sourcing 0.04 0.1 V
VHB-UVLO HB-SW UVLO threshold HB-SW falling 2.2 2.5 3.0 V
IHB-SLEEP HB quiescent current in sleep HB-SW = 5V 3.5 7 µA
tDHL HO off to LO on deadtime 20 ns
tDLH LO off to HO on deadtime 22 ns
HB diode resistance 1.2 Ω
THERMAL SHUTDOWN
TTSD-RISING Thermal shutdown threshold Temperature rising 175 °C
TTSD-HYS Thermal shutdown hysteresis 15 °C