SNOSD87A July   2021  – February 2022 LM74501-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage
      2. 8.3.2 Charge Pump
      3. 8.3.3 Enable
      4. 8.3.4 Gate Driver
      5. 8.3.5 SW (Battery Voltage Monitoring)
      6. 8.3.6 Gate Discharge Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Full Conduction Mode
      3. 8.4.3 VDS Clamp
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reverse Battery Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 MOSFET Selection
        3. 9.2.2.3 Gate Discharge Timer Capacitor Selection (CT)
        4. 9.2.2.4 Charge Pump VCAP, Input and Output Capacitance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.3 Gate Discharge Timer Capacitor Selection (CT)

A gate discharge timer decides the time duration for which external MOSFET is kept on after the LM74501-Q1 fall below its PoR threshold (VPORF) or when EN pin is pulled low. A ISO7637-2 pulse 1 transient lasts for typically 2 ms. At the end of 2-ms ISO7637-2 pulse 1, amplitude has already fallen to 10% of its peak value. Assuming a ISO7637-2 pulse 1 transient with amplitude of –150 V, at the end of 2 ms, the voltage seen by the LM74501-Q1 is around –15 V. With a VDS rating of external MOSFET of 40 V, the gate discharge timer capacitor, CT, can be selected such that external FET remains on for less than 2 ms. A CT timer capacitor value of 22 nF is selected for the given MOSFET as per Equation 2.