SNOSD98A May   2020  – December 2020 LM7481-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Over Voltage Protection and Battery Voltage sensing (VSNS, SW, OV)
      4. 8.3.4 Low Iq Shutdown and Under Voltage Lockout (EN/UVLO)
    4. 8.4 Device Functional Modes
    5. 8.5 Application Examples
      1. 8.5.1 Redundant Supply OR-ing with Inrush Current Limiting, Over Voltage Protection and ON/OFF Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1  Design Requirements for 12-V Battery Protection
      2. 9.2.2  Automotive Reverse Battery Protection
      3. 9.2.3  Input Transient Protection: ISO 7637-2 Pulse 1
      4. 9.2.4  AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
      5. 9.2.5  Input Micro-Short Protection: LV124 E-10
      6. 9.2.6  Detailed Design Procedure
        1. 9.2.6.1 Design Considerations
        2. 9.2.6.2 Charge Pump Capacitance VCAP
        3. 9.2.6.3 Input and Output Capacitance
        4. 9.2.6.4 Hold-up Capacitance
        5. 9.2.6.5 Over Voltage Protection and Battery Monitor
      7. 9.2.7  MOSFET Selection: Blocking MOSFET Q1
      8. 9.2.8  MOSFET Selection: Hot-Swap MOSFET Q2
      9. 9.2.9  TVS selection
      10. 9.2.10 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 TVS Selection for 12-V Battery Systems
    3. 10.3 TVS Selection for 24-V Battery Systems
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) =  V(OUT) = V(VS) = V(VSNS) = 12 V, V(AC) = 20 mV, C(VCAP) = 0.1 µF, V(EN/UVLO) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
V(VS) Operating input voltage 3 65 V
V(VS_PORR) VS POR threshold, rising 2.4 2.6 2.85 V
V(VS_PORF) VS POR threshold, falling 1.9 2.1 2.3 V
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V 2.87 5 µA
I(Q) Total System Quiescent current, I(GND) V(EN/UVLO) = 2 V 396 µA
V(A) =  V(VS) = 24 V,  V(EN/UVLO) = 2 V 408 480 µA
I(REV) I(A)  leakage current during Reverse Polarity, 0 V ≤ V(A) ≤ – 65 V 19 112 µA
I(OUT) leakage current during Reverse Polarity 1 µA
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(UVLOR) EN/UVLO threshold voltage, rising 1.195 1.231 1.267 V
V(UVLOF) EN/UVLO threshold voltage, falling 1.091 1.132 1.159 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.3 0.67 0.93 V
V(EN_Hys) Enable Hysteresis 37 72 95 mV
I(EN/UVLO) 0 V ≤ V(EN/UVLO) ≤  65 V 52 200 nA
OVER VOLTAGE PROTECTION AND BATTERY SENSING (VSNS, SW, OV) INPUT
R(SW) Battery sensing disconnect switch resistance 3 V ≤ V(SNS) ≤ 65 V 10 19.5 46 Ω
V(OVR) Overvoltage threshold input, rising 1.195 1.231 1.267 V
V(OVF) Overvoltage threshold input, falling 1.091 1.13 1.159 V
I(OV) OV Input leakage current 0 V ≤ V(OV) ≤ 65 V 53 200 nA
CHARGE PUMP (CAP)
I(CAP) Charge Pump source current (Charge pump on) V(CAP) – V(A) = 7 V, 6 V ≤ V(S) ≤ 65 V 2.5 3.8 mA
VCAP – VS Charge Pump Turn ON voltage 11 12.2 13.2 V
Charge Pump Turnoff voltage 11.9 13.2 14.1 V
V(CAP UVLO) Charge Pump UVLO voltage threshold, rising 5.4 6.6 7.9 V
Charge Pump UVLO voltage threshold, falling 4.4 5.5 6.6 V
IDEAL DIODE (A, C, DGATE)
V(A_PORR) V(A) POR threshold, rising 2.2 2.35 2.6 V
V(A_PORF) V(A) POR threshold, falling 2 2.2 2.4 V
V(AC_REG) Regulated Forward V(A)–V(C) Threshold 5.8 9.1 12.4 mV
V(AC_REV) V(A)–V(C) Threshold for Fast Reverse Current Blocking –6.4 –4 –1.3 mV
V(AC_FWD) V(A)–V(C) Threshold for Reverse to Forward transition 150 177 200 mV
V(DGATE) – V(A) Gate Drive Voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 10 11.5 13 V
I(DGATE) Peak Gate Source current V(A) – V(C) = 100 mV, V(DGATE) – V(A) = 1 V 60 mA
Peak Gate Sink current V(A) – V(C) = –12 mV, V(DGATE) – V(A) = 11 V 2670 mA
Regulation sink current V(A) – V(C) = 0 V, V(DGATE) – V(A) = 11 V 8.4 14.9 µA
I(C) Cathode leakage Current V(A) = –14 V, V(C) = 12 V 4 9 32 µA
HIGH SIDE CONTROLLER (HGATE, OUT, SNS, SW, OV)
V(HGATE) – V(OUT) Gate Drive Voltage 3 V < V(S) < 5 V 7 V
5 V < V(S) < 65 V 10 11.1 14.5 V
I(HGATE) Source Current 39 55 75 µA
Sink Current V(OV) > V(OVR) 168 260 mA