SNAS461G May   2010  – November 2018 LM98640QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings    
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information         
    5. 6.5 Quality Conformance Inspection
    6. 6.6 LM98640QML-SP Electrical Characteristics
    7. 6.7 AC Timing Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sampling Modes
        1. 7.3.1.1 Sample & Hold Mode
          1. 7.3.1.1.1 Sample & Hold Mode CLAMP/SAMPLE Adjust
        2. 7.3.1.2 CDS Mode
          1. 7.3.1.2.1 CDS Mode Bimodal Offset
          2. 7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
      2. 7.3.2 Input Bias and Clamping
        1. 7.3.2.1 Sample and Hold Mode Biasing
        2. 7.3.2.2 CDS Mode Biasing
        3. 7.3.2.3 VCLP DAC
      3. 7.3.3 Programmable Gain
        1. 7.3.3.1 CDS/SH Stage Gain
        2. 7.3.3.2 PGA Gain Plots
      4. 7.3.4 Programmable Analog Offset Correction
      5. 7.3.5 Analog to Digital Converter
      6. 7.3.6 LVDS Output
        1. 7.3.6.1 LVDS Output Voltage
        2. 7.3.6.2 LVDS Output Modes
        3. 7.3.6.3 TXFRM Output
          1. 7.3.6.3.1 Output Mode 1 - Dual Lane
          2. 7.3.6.3.2 Output Mode 2 - Quad Lane
      7. 7.3.7 Clock Receiver
      8. 7.3.8 Power Trimming
    4. 7.4 Device Functional Mode
      1. 7.4.1 Powerdown Modes
      2. 7.4.2 LVDS Test Modes
        1. 7.4.2.1 Test Mode 0 - Fixed Pattern
        2. 7.4.2.2 Test Mode 1 - Horizontal Gradient
        3. 7.4.2.3 Test Mode 2 - Vertical Gradient
        4. 7.4.2.4 Test Mode 3 - Lattice Pattern
        5. 7.4.2.5 Test Mode 4 - Stripe Pattern
        6. 7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
        7. 7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
        8. 7.4.2.8 Pseudo Random Number Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Writing to the Serial Registers
      3. 7.5.3 Reading the Serial Registers
      4. 7.5.4 Serial Interface Timing Details
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Total Ionizing Dose
      2. 8.1.2 Single Event Latch-Up and Functional Interrupt
      3. 8.1.3 Single Event Effects
    2. 8.2 Typical Application
      1. 8.2.1 Sample/Hold Mode
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power Planes
      2. 9.1.2 Bypass Capacitors
      3. 9.1.3 Ground Plane
      4. 9.1.4 Thermal Management
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Board
        2. 10.1.1.2 Register Programming Software
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Export Control Notice
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NBB|68
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Maps

Registers need to be written with baseline values after power-up to place part in a valid state.

Table 5. Configuration Registers

ADDRESS
(BINARY)		 REGISTER TITLE
(MNEMONIC)		 BASELINE
(BINARY)		 REGISTER and BIT DESCRIPTION
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ANALOG CONFIGURATION
00 0000 Main Configuration 0000 0100 Not Used Coarse DAC Enable Fine DAC Enable Reserved CLPIN Gating Enable CDS Gain Enable Reserved CDS Enable
00 0001 Powerdown Control 0000 0000 Master Powerdown VCLP Powerdown Ch2 Ref Buf Powerdown Ch1 Ref Buf Powerdown Ch2 PGA Powerdown Ch1 PGA Powerdown Ch2 ADC Powerdown Ch1 ADC Powerdown
00 0010 PGA Power Trimming 0010 0100 Reserved PGA Stage 2 Bias Current Trimming PGA Stage 1 Bias Current Trimming
00 0011 ADC Power Trimming 0101 1011 Reserved ADC Current Trimming 2 ADC Current Trimming 1
00 0100 VCLP Control 0111 0100 Not Used Buffer Enable VCLP Enable VCLP Voltage Level
00 0101 LVDS Output Modes 0000 1110 Clear Reserved Reserved Reserved Quad Lane Enable LVDS Enable LVDS Control
00 0110 Sample & Hold 1000 0001 S/H Enable Not Used Ref Buf Power Level Reserved
00 0111 Status 0000 0000 Not Used False Lock
00 1000 Reserved 0000 0000 Reserved
00 1001 Clock Monitor 0000 0000 Not Used Enable/Select Not Used
00 1010 Reserved 0000 0000 Not Used
00 1011 Reserved 0000 0000 Not Used
00 1100 Reserved 0000 0000 Not Used
00 1101 Reserved 0000 0000 Not Used
00 1110 Reserved 0000 0000 Not Used
00 1111 Reserved 0000 0000 Not Used
GAIN & OFFSET DAC CONFIGURATION
01 0000 CDAC1 0000 0000 Not Used Offset bit 8
01 0001 CDAC1 1111 1111 Offset Value bits 7:0
01 0010 FDAC1 0000 0000 Not Used Offset bit 8
01 0011 FDAC1 1111 1111 Offset Value bits 7:0
01 0100 Reserved 0000 0000 Not Used
01 0101 PGA1 0110 0001 PGA Gain Value
01 0110 Reserved 0000 0000 Not Used
01 0111 Reserved 0000 0000 Not Used
01 1000 CDAC2 0000 0000 Not Used Offset Bit 8
01 1001 CDAC2 1111 1111 Offset Value bits 7:0
01 1010 FDAC2 0000 0000 Not Used Offset Bit 8
01 1011 FDAC2 1111 1111 Offset Value bits 7:0
01 1100 PGA2 0110 0001 PGA Gain Value
01 1101 Reserved 0000 0000 Not Used
01 1110 Reserved 0000 0000 Not Used
01 1111 Reserved 0000 0000 Not Used
TIMING CONFIGURATION
10 0000 Clamp Start 0000 1000 Not Used Clamp Start Index
10 0001 Clamp End 0001 1100 Not Used Clamp End Index
10 0010 Sample Start 0010 1000 Not Used Sample Start Index
10 0011 Sample End 0011 1100 Not Used Sample End Index
10 0100 Reserved 0011 0100 Reserved
10 0101 INCLK Range 0000 0010 Not Used INCLK Range Not Used Reserved
10 0110 Reserved 0000 0000 Not Used
10 0111 Reserved 0000 0000 Not Used
10 1000 DLL Configuration 0000 1111 Reserved DLL Reset
10 1001 Reserved 0000 0000 Not Used
10 1010 Reserved 0000 0000 Not Used
10 1011 Reserved 0000 0000 Not Used
10 1100 Reserved 0000 0000 Not Used
10 1101 Reserved 0000 0000 Not Used
10 1110 Reserved 0000 0000 Not Used
10 1111 Reserved 0000 0000 Not Used
DIGITAL CONFIGURATION REGISTERS
11 0000 Test Pattern Start 0000 0000 Start Upper Bits
11 0001 Test Pattern Start 0000 0000 Start Lower Bits
11 0010 Test Pattern Width 0000 0000 Width Upper Bits
11 0011 Test Pattern Width 0000 0000 Width Lower Bits
11 0100 Test Pattern Control 0000 0000 Pattern Enable Pattern Mode Pseudo Random Enable Seed Enable Pattern Output Channel
11 0101 Test Pattern Pitch 0000 0000 Test Pattern Pitch
11 0110 Test Pattern Step 0000 0000 Test Pattern Step Code
11 0111 Test Pattern Channel Offset 0000 0000 Not Used Test Pattern Channel Offset
11 1000 Test Pattern Value 0000 0000 Pattern Upper Bits
11 1001 Test Pattern Value 0000 0000 Pattern Lower Bits
11 1010 Reserved 0000 0000 Not Used
11 1011 Reserved 0000 0000 Not Used
11 1100 Digital Configuration 0000 0000 Not Used Auto Read
11 1101 Test & Scan Control 0000 0000 Not Used Pattern Voting Enable U-Wire Voting Enable Not Used Test Reset Test Mode Not Used
11 1110 Device ID 0100 1000 Device Revision ID. Engineering samples might be x01 or x47.
11 1111 Reserved 0000 0000 Not Used