SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)

The SYSREF outputs within the clock output channels have the same output buffer structure as the clock output buffer, with the addition of circuitry to adjust the common-mode voltage. The SYSREF outputs are CML outputs with a common-mode voltage that can be adjusted with the SYSREFOUTx_VCM field, and the output level that can be programmed with the SYSREFOUTx_PWR field. This is to allow DC coupling. Note that the CLKOUT outputs do not have adjustable common-mode voltage and must be AC coupled; this is for optimal noise performance.

GUID-20220808-SS0I-X5R1-W27Z-BFP9CJJVJM0C-low.svg Figure 6-7 SYSREF Output Buffer

The common-mode voltage and output power are interrelated and can be simulated assuming a 100-Ω differential load and no DC path to ground. The common mode voltage and output are interrelated as shown in Table 6-9. Note that for long-term reliability reasons, it is required that VCM – VOD/2 ≥ 0.5 V.

Table 6-9 Single-Ended Voltage (VOD) and Common-Mode Voltage (VCM)
SYSREFOUT_PWR Check:VCM - VOL/2 ≥ 0.5 V. ? SYSREFOUT_VCM VOD VCM
0 Valid State 0 0.27 1.09
1 0.27 1.22
2 0.28 1.37
3 0.28 1.54
4 0.29 1.69
5 0.29 1.83
6 0.29 2.00
7 0.29 2.16
1 0 0.32 0.79
1 0.33 0.95
2 0.33 1.12
3 0.34 1.33
4 0.35 1.51
5 0.35 1.69
6 0.36 1.89
7 0.37 2.08
2 Invalid State 0 0.37 0.52
1 0.38 0.68
Valid State 2 0.39 0.89
3 0.40 1.12
4 0.41 1.34
5 0.42 1.54
6 0.43 1.78
7 0.44 2.01
3 Invalid State 0 0.39 0.43
1 0.42 0.50
2 0.45 0.66
Valid State 3 0.46 0.93
4 0.47 1.17
5 0.48 1.41
6 0.49 1.68
7 0.51 1.93
4 Invalid State 0 0.40 0.40
1 0.43 0.44
2 0.48 0.52
3 0.51 0.73
Valid State 4 0.52 1.00
5 0.54 1.27
6 0.55 1.57
7 0.57 1.86
5 Invalid State 0 0.40 0.38
1 0.44 0.42
2 0.49 0.47
3 0.55 0.59
Valid State 4 0.58 0.85
5 0.59 1.14
6 0.62 1.48
7 0.63 1.79
6 Invalid State 0 0.40 0.36
1 0.44 0.39
2 0.49 0.45
3 0.57 0.54
4 0.63 0.70
Valid State 5 0.65 1.01
6 0.67 1.38
7 0.70 1.73
7 Invalid State 0 0.40 0.35
1 0.44 0.38
2 0.50 0.43
3 0.58 0.51
4 0.66 0.62
Valid State 5 0.70 0.89
6 0.73 1.29
7 0.76 1.66