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LMX1906-SP

ACTIVE

Radiation-hardened, QML-P, 15GHz buffer, multiplier and divider with SYSREF and FPGA clock

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Data sheet

LMX1906-SP

ACTIVE
Data sheet Order now

Product details

Frequency (max) (MHz) 15000 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Space Qualified, Space grade, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -55 to 125 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 15000 Frequency (min) (MHz) 300 Features Integrated multiplier and divider modes, JESD204B/C SYSREF support, Phase synchronization, RF clock distribution, Radiation hardened, Space Qualified, Space grade, Ultra-low additive jitter Current consumption (mA) 405 Integrated VCO No Operating temperature range (°C) -55 to 125 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
HTQFP (PAP) 64 144 mm² (12 mm × 12 mm)
  • SMD #5962-23202
    • Total ionizing dose 100krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 87MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 87MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • SMD #5962-23202
    • Total ionizing dose 100krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 87MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 87MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature

The LMX1906-SP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.

The LMX1906-SP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet LMX1906-SP Space Grade Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider datasheet (Rev. A) PDF | HTML May 20, 2025
* Radiation & reliability report LMX1906-SP Total Ionizing Dose Report PDF | HTML Jan 5, 2024
* Radiation & reliability report LMX1906-SP Single Event Effects Report Nov 15, 2023
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML Jun 17, 2025
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML Apr 11, 2025
Certificate LMX1906EVM-CVAL EU Declaration of Conformity (DoC) PDF | HTML Sep 14, 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMX1906EVM-CVAL — LMX1906-SP evaluation module

The LMX1906-SP evaluation module (EVM) is designed to evaluate the performance of the LMX1906-SP, which is a four-output, ultra-low additive jitter radio-frequency (RF) buffer, divider and multiplier. The device can buffer RF frequencies up to 18GHz, multiply RF outputs up to 6.4GHz and divide (...)
User guide: PDF | HTML
Supported products & hardware
Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware
Simulation model

LMX1906-SP IBIS Model

SNAM300.ZIP (61 KB) - IBIS model
Supported products & hardware
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
HTQFP (PAP) 64 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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