SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Characteristics

If not otherwise, the following conditions can be assumed: Temperature = 25°C, Vcc = 2.5 V, OUTx_PWR=5, CLKIN driven differentially with 8 dBm at each pin. Signal source used was SMA100B with ultra-low noise option B711.
GUID-20231101-SS0I-RL5L-FDFM-ZBJGX1W7LWBR-low.svg
Noise Floor = –160 dBc/Hz 
Figure 5-2 Buffer Phase Noise Plot at 6 GHz Output
GUID-20231031-SS0I-26RM-CFQT-BH6GL157ZT7X-low.svg
Figure 5-4 Multiplier Phase Noise Plot at 6 GHz Output
GUID-20231215-SS0I-K8NS-TXKQ-486RZTDP1RCM-low.svg
Figure 5-6 LMX1906-SP Flicker Noise
GUID-20231101-SS0I-SKG2-1DTG-WJTM2HXHS4RN-low.svg
Input power is differential
Figure 5-8 Noise Floor in Multiply x2 Mode
GUID-20231101-SS0I-R4KB-7KPJ-ND2THKMWSHLX-low.svg
CLKOUTx_PWR = 7
Figure 5-10 Buffer Mode Single-Ended Output Power
GUID-20231101-SS0I-MKBP-F9V8-JP7F0X85WM3N-low.svg
Figure 5-12 Multiplier 1/2 Sub-Harmonic in X2 Mode
GUID-20231215-SS0I-34HH-RM58-FFWQBFSDFLP4-low.svg
Figure 5-14 Second Harmonic on Divider Mode (Single-Ended Input)
GUID-20231215-SS0I-DSMQ-LK21-VQ6WBSJKQR6T-low.svg
 
 
Figure 5-16 SYSREF Delta Delay vs. Code
GUID-20231215-SS0I-F1LM-2SVG-FK2PSSGKMQWR-low.svg
Figure 5-18 Propagation Delay
GUID-20231215-SS0I-LHV6-MRDN-X2ZZVTMT9BX1-low.svg
Figure 5-20 Channel Disable Setting Time
GUID-20231031-SS0I-Z33V-PRTT-X1ZKTDQPJS7F-low.svg
Noise Floor = –159.8 dBc/Hz
Figure 5-3 Divider Phase Noise Plot at 6 GHz Output (Divide by 2)
GUID-20231101-SS0I-CHTM-PWJG-SL8GGCTNJ3XV-low.svg
 Stated input power is applied at each pin
Figure 5-5 Noise Floor in Buffer Mode
GUID-20231101-SS0I-GXR9-1TVL-ZLTT6WKLFCGW-low.svg
 
Figure 5-7 Noise Floor in Buffer Mode
GUID-20231101-SS0I-PSF4-7W3C-KTDPHHLWQ62V-low.svg
Applies to all modes except divider mode with odd divide (which will have slightly lower power).
Figure 5-9 Buffer Mode Single-Ended Output Power
GUID-20231101-SS0I-KZ1S-TD6Z-XNPRXBHQ7PVM-low.svg
Figure 5-11 Second Harmonic in Multiply X2 Mode (Differential Output)
GUID-20231101-SS0I-KNPD-7M4H-KVSQVTQZGZWP-low.svg
Output is differential.
Figure 5-13 Multiplier Sub-Harmonics (Harmonic Frequency = Output Frequency / M )
GUID-20231215-SS0I-JTNZ-7XPN-HDNCXTQHXXCG-low.svg
Figure 5-15 Output to Output Skew (ps)
GUID-20231215-SS0I-NTXS-9JBP-GKXBWZ71HP0Z-low.svg
Measured in power-down mode to make Junction Temperature = Ambient Temperature.
Figure 5-17 Temperature Sensor Readback
GUID-20231215-SS0I-6D4C-XG56-7V8C41HJXDMR-low.svg
 
 
 
Figure 5-19 Channel Enable Setting Time