SNOSA40K November   2002  – December 2016 LP2996-N , LP2996A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Normal Operation
      3. 7.4.3 Shutdown
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical SSTL-2 Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
          1. Input Capacitor
          2. Output Capacitor
            1. Aluminum Electrolytics
            2. Ceramic Capacitors
            3. Hybrid Capacitors
            4. PC Application Considerations
        3. Application Curves
      2. 8.2.2 Other Application Circuits
        1. SSTL-2 Applications
        2. DDR-II Applications
        3. DDR-III Applications
      3. 8.2.3 Level Shifting
      4. 8.2.4 HSTL Applications
      5. 8.2.5 QDR Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown


  • LP2996-N: DDR1 and DDR2 Termination Voltage
  • LP2996A: DDR1, DDR2, DDR3, and DDR3L Termination Voltage
  • FPGA
  • Industrial and Medical PC
  • SSTL-2 and SSTL-3 Termination
  • HSTL Termination


The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

Device Information(1)

LP2996-N SOIC (8) 4.90 mm x 3.90 mm
LP2996-N, LP2996A WSON (8) 4.90 mm x 3.90 mm
LP2996-N WQFN (16) 4.00 mm x 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

LP2996-N LP2996A 20057518.gif

Revision History

Changes from J Revision (March 2013) to K Revision

  • Added Device Information table, Specifications section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Added LP2996A throughout data sheetGo
  • Added DDR3 support throughout data sheetGo
  • Deleted Lead temperature (260°C maximum) from Absolute Maximum RatingsGo
  • Changed Thermal Resistance, RθJA, values in Thermal Information From: 151°C/W To: 119.5°C/W (SOIC), From: 151°C/W To: 56.5°C/W (SO), and From: 151°C/W To: 52.7°C/W (WQFN)Go

Changes from I Revision (March 2013) to J Revision

  • Changed layout of National Semiconductor Data Sheet to TI formatGo
  • Added VDDQ RangeGo