SNOSA40K November   2002  – December 2016 LP2996-N , LP2996A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Normal Operation
      3. 7.4.3 Shutdown
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical SSTL-2 Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
            1. 8.2.1.2.2.1 Aluminum Electrolytics
            2. 8.2.1.2.2.2 Ceramic Capacitors
            3. 8.2.1.2.2.3 Hybrid Capacitors
            4. 8.2.1.2.2.4 PC Application Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Other Application Circuits
        1. 8.2.2.1 SSTL-2 Applications
        2. 8.2.2.2 DDR-II Applications
        3. 8.2.2.3 DDR-III Applications
      3. 8.2.3 Level Shifting
      4. 8.2.4 HSTL Applications
      5. 8.2.5 QDR Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
DDA Package
8-Pin SO With PowerPAD
Top View
NHP Package
16-Pin WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME SO PowerPAD SOIC WQFN
AVIN 6 6 10 I Analog input pin. AVIN is used to supply all the internal control circuitry. This pin has the capability to work from a supply separate from PVIN depending on the application. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the requirement for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN.
GND 1 1 2 — Ground
PVIN 7 7 11, 12 I Power input pin. PVIN is used exclusively to provide the rail voltage for the output stage used to create VTT. This pin has the capability to work from a supply separate from PVIN depending on the application. Higher voltages on PVIN increases the maximum continuous output current because of output RDS(ON) limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss also increases, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the requirement for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. TI recommends connecting PVIN to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown then the part enters a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active.
SD 2 2 4 I Shutdown. The LP2996-N and LP2996A contain an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT must not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current of the LP2996-N and LP2996A drops, however, VDDQ always maintains its constant impedance of 100 kΩ for generating the internal reference. Therefore, to calculate the total power loss in shutdown, both currents must be considered. See Thermal Considerations for more information. The shutdown pin also has an internal pullup current, therefore to turn the part on, the shutdown pin can either be connected to AVIN or left open.
VDDQ 5 5 8 I Input for internal reference equal to VDDQ / 2. VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50-kΩ resistors. This ensures that VTT tracks VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5-V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ is a 2.5-V signal, which creates a 1.25-V termination voltage at VTT. See Electrical Characteristics for exact values of VTT over temperature.
VREF 4 4 7 O Buffered internal reference voltage of VDDQ / 2. VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output must be used to provide the reference voltage for the Northbridge chipset and memory. Because these inputs are typically an extremely high impedance, there must be little current drawn from VREF. For improved performance, an output bypass capacitor can be placed close to the pin to help reduce noise. TI recommends a ceramic capacitor from 0.1 µF to 0.01 µF. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality.
VSENSE 3 3 5 I Feedback pin for regulating VTT. The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors connect to VTT in a long plane. If the output voltage was regulated only at the output of the device then the long trace causes a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance by connecting it to the middle of the bus. This provides a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Take care when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1-µF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.
VTT 8 8 14, 15 O Output voltage for connection to termination resistors. VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2996-N and LP2996A are designed to handle peak transient currents of up to ±3 A with a fast transient response. The maximum continuous current is a function of VDD and can be seen in Typical Characteristics. If a transient above the maximum continuous current rating is expected to last for a significant amount of time then the output capacitor must be large enough to prevent an excessive voltage drop. Despite the fact that the device is designed to handle large transient output currents it is not capable of handling these for long durations under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then ensure that the maximum junction temperature is not exceeded. Proper thermal derating must always be used (see Thermal Considerations). If the junction temperature exceeds the thermal shutdown point then VTT tri-states until the part returns below the hysteretic trip-point.
NC — — 1, 3, 6, 9, 13, 16 — No internal connection
Thermal Pad PowerPAD — Thermal Pad — Exposed pad thermal connection. Connect to Ground.