8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

8.2.1.2 Detailed Design Procedure

The LP2996 requires voltage be applied to three pins for proper operation: VDDQ, AVIN, and PVIN. VDDQ sets the internal reference voltage and is divided across two 50-kΩ resistors. Therefore, VDDQ must be set at exactly twice the appropriate DDR termination. AVIN powers the internal control circuitry and must be from 2.2 V to
5.5 V. PVIN is the supply for the power output stage and must be larger than or equal to VDDQ while smaller than or equal to AVIN. When picking PVIN, note that smaller values reduce internal power dissipation but reduce the maximum continuous current as well. It is acceptable to tie PVIN to either VDDQ or AVIN to minimize the number of supplies and bypass capacitors required.

To prevent voltage dips on the output, a bypass capacitor must be placed on the VTT line. The size of this capacitor does not affect stability, but larger values improve the transient response and must be sized according to the design requirements. When using ceramic capacitors on the output, large load steps can cause ringing on VTT. Table 2 shows the range of acceptable equivalent series resistance (ESR) that can be added to dampen and improve the response.

Another bypass capacitor on PVIN is recommended to keep current spikes from pulling down the input voltage. This is especially important if PVIN and VDDQ are on the same supply. A small 0.01-µF capacitor can be placed on VREF to reduce noise. VSENSE provides a feedback path necessary for regulating the output voltage; Therefore, it must be connected to VTT. If a long VSENSE trace is necessary, a small ceramic capacitor may be required to filter out any high frequency noise picked up from switching I/O signals.

8.2.1.2.2 Output Capacitor

The LP2996-N and LP2996A have been designed to be insensitive of output capacitor size or ESR. This allows the flexibility to use any capacitor desired. The choice for output capacitor is determined solely on the application and the requirements for load transient response of V_TT. TI recommends the output capacitor be sized above
100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR is determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are discussed: Aluminum Electrolytics, Ceramic Capacitors, and Hybrid Capacitors.

8.2.1.2.2.1 Aluminum Electrolytics

Aluminum electrolytics often only specify impedance at a frequency of 120 Hz, indicating poor high frequency performance. Only aluminum electrolytics that specified an impedance at higher frequencies, from 20 kHz to
100 kHz, must be used for the LP2996-N and LP2996A. To improve the ESR, many aluminum electrolytics may be combined in parallel for an overall reduction. Be aware of the extent at which the ESR changes over temperature. Aluminum electrolytic capacitors' ESR may rapidly increase at cold temperatures.

8.2.1.2.2.2 Ceramic Capacitors

Ceramic capacitors typically have a low capacitance, from 10 µF to 100 µF, but they have excellent AC performance for bypassing noise due to very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance, TI recommends using ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. TI recommends dielectric of X5R or better for all ceramic capacitors.

8.2.1.2.2.3 Hybrid Capacitors

Hybrid capacitors offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than any other capacitor.

8.2.1.2.2.4 PC Application Considerations

With motherboards and other applications where V_TT is distributed across a long plane, it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. Figure 19 shows an example circuit where two bulk output capacitors could be situated at both ends of the V_TT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost.

In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitors approximately 1000 µF are typically used.

Figure 19. Typical SSTL-2 Application Circuit for Motherboards

8.2.1.3 Application Curves

Figure 20. 0.5-A Load Transient With 220-µF V_TT Capacitor

Figure 21. 1.5-A Load Transient With 220-µF V_TT Capacitor

8.2.2.1 SSTL-2 Applications

For the majority of applications that implement the SSTL-2 termination scheme, TI recommends connecting all the input rails to the 2.5-V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 22.

Figure 22. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern, then the LP2996-N or LP2996A has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5 V, 3.3 V, or 5 V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients are encountered.

Figure 23. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8-V rail is not available and it is not desirable to use 2.5 V, is to connect the LP2996-N or LP2996A power rail to 3.3 V. In this situation AVIN is limited to operation on the 3.3-V or 5-V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Prevent the device from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk, TI recommends not supplying the output stage with a voltage higher than a nominal 3.3-V rail.

Figure 24. SSTL-2 Implementation with Higher Voltage Rails

8.2.2.2 DDR-II Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N and LP2996A in applications utilizing DDR-II memory. Figure 25 and Figure 26 show implementations of recommended circuit configurations for DDR-II applications. The output stage is connected to the 1.8-V rail and the AVIN pin can be connected to either a 3.3-V or 5-V rail. TI recommends the LP2996A, LP2998, or LP2998-Q1 for DDR-III and DDR-III low power designs.

Figure 25. Recommended DDR-II Termination

If it is not desirable to use the 1.8-V rail it is possible to connect the output stage to a 3.3-V rail. Take care not to exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason, TI does not recommend powering PVIN from a rail higher than the nominal 3.3 V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.

Figure 26. DDR-II Termination with Higher Voltage Rails

8.2.2.3 DDR-III Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996A in applications utilizing DDR-III memory. The output stage is connected to the 1.5-V rail and the AVIN pin can be connected to a 2.2-V to 5.5-V rail.

Figure 27. Recommended DDR-III Termination Using the LP2996A

If it is not desirable to use the 1.5-V to 2.5-V rail it is possible to connect the output stage to a 3.3-V rail. Do not exceed the maximum junction temperature as the thermal dissipation increases with lower V_TT output voltages. For this reason, TI recommends not to power PVIN off a rail higher than the nominal 3.3-V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.