Top

Product details

Parameters

DDR memory type DDR, DDR2 Control mode Iout VTT (Max) (A) 1.5 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 1.8 Vin (Max) (V) 5.5 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (C) 0 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 4.9 x 3.9 WQFN (NHP) 16 16 mm² 4 x 4 open-in-new Find other DDR memory power ICs

Features

  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown
open-in-new Find other DDR memory power ICs

Description

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

open-in-new Find other DDR memory power ICs
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet LP2996-N, LP2996A DDR Termination Regulator datasheet (Rev. K) Dec. 23, 2016
Application note Limiting DDR Termination Regulators’ Inrush Current Aug. 23, 2016
User guide AN-1268 LP2996 Evaluation Board (Rev. A) May 07, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description

The LP2996 evaluation board is designed to provide the design engineer with a fully functional prototype system in which to evaluate the LP2996 in both a static environment and with a complete memory system. There are two versions of the board, and while identical in functionality they differ in the (...)

Features
  • Source and sink current
  • Low output voltage offset
  • No external resistors required
  • Linear topology
  • Suspend to Ram (STR) functionality
  • Low external component count
  • Thermal shutdown
  • Available in PSOP-8 package

Applications:

  • DDR-I and DDR-II Termination Voltage
  • SSTL-2 and SSTL-3 Termination
  • HSTL Termination

 

EVALUATION BOARD Download
10
Description

The LP2996 evaluation board is designed to provide the design engineer with a fully functional prototype system in which to evaluate the LP2996 in both a static environment and with a complete memory system. There are two versions of the board, and while identical in functionality they differ in the (...)

Features
  • Source and sink current
  • Low output voltage offset
  • No external resistors required
  • Linear topology
  • Suspend to Ram (STR) functionality
  • Low external component count
  • Thermal shutdown
  • Available in PSOP-8 package

Applications:

  • DDR-I and DDR-II Termination Voltage
  • SSTL-2 and SSTL-3 Termination
  • HSTL Termination

 

Design tools & simulation

SIMULATION MODEL Download
SNOM563.ZIP (82 KB) - PSpice Model
SIMULATION MODEL Download
SNOM566.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options
SOIC (D) 8 View options
WQFN (NHP) 16 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos