SNVSAT4A September 2017 – June 2021 LP873220-Q1
There are two reset methods implemented on the LP873220-Q1:
An software reset occurs when 1 is written to the SW_RESET bit. The bit is automatically cleared after writing. This event disables all the regulators immediately, drives the GPO or GPO2 signals low, resets all the register bits to the default values, and loads the OTP bits (see Figure 7-13). The I2C interface is not reset during a software reset.
If the VANA supply voltage falls below the UVLO threshold level, then all the regulators are disabled immediately, the GPO or GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA supply voltage transitions above the UVLO threshold level, an internal POR occurs. The OTP bits are loaded to the registers and a startup is initiated according to the register settings.