The power-up sequence for the LP873220-Q1 is as follows:
- The VANA and VIN_Bx reach minimum recommended levels (VVANA > VANAUVLO). This initiates power-on-reset (POR), OTP reading, and enables the system I/O interface. The I2C host should allow at least 1.2 ms before writing or reading data to the LP873220-Q1.
- The device enters standby mode.
- The host can change the default register setting by I2C if needed.
- The regulators can be enabled and disabled.
- The GPO signals can be controlled by the EN pin and the I2C interface.
Transitions between the operating modes are shown in Section 7.4.1.