SNVSC24 April   2021 LP8758-EA


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
        1. Operating Modes
        2. Programmability
        3. Features
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overview
        1. Transition Between PWM and PFM Modes
        2. Buck Converter Load Current Measurement
        3. Spread-Spectrum Mode
      2. 7.3.2 Power-Up
      3. 7.3.3 Regulator Control
        1. Enabling and Disabling
        2. Changing Output Voltage
      4. 7.3.4 Device Reset Scenarios
      5. 7.3.5 Diagnosis and Protection Features
        1. Warnings for Diagnosis (Interrupt)
          1. Output Current Limit
          2. Thermal Warning
        2. Protection (Regulator Disable)
          1. Short-Circuit and Overload Protection
          2. Thermal Shutdown
        3. Fault (Power Down)
          1. Undervoltage Lockout
      6. 7.3.6 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.  OTP_REV
        2.  BUCK0_CTRL1
        3.  BUCK0_CTRL2
        4.  BUCK1_CTRL1
        5.  BUCK1_CTRL2
        6.  BUCK2_CTRL1
        7.  BUCK2_CTRL2
        8.  BUCK3_CTRL1
        9.  BUCK3_CTRL2
        10. BUCK0_VOUT
        11. BUCK0_FLOOR_VOUT
        12. BUCK1_VOUT
        13. BUCK1_FLOOR_VOUT
        14. BUCK2_VOUT
        15. BUCK2_FLOOR_VOUT
        16. BUCK3_VOUT
        17. BUCK3_FLOOR_VOUT
        18. BUCK0_DELAY
        19. BUCK1_DELAY
        20. BUCK2_DELAY
        21. BUCK3_DELAY
        22. RESET
        23. CONFIG
        24. INT_TOP
        25. INT_BUCK_0_1
        26. INT_BUCK_2_3
        27. TOP_STAT
        28. BUCK_0_1_STAT
        29. BUCK_2_3_STAT
        30. TOP_MASK
        31. BUCK_0_1_MASK
        32. BUCK_2_3_MASK
        33. SEL_I_LOAD
        34. I_LOAD_2
        35. I_LOAD_1
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Application Components
          1. Inductor Selection
          2. Input Capacitor Selection
          3. Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The high frequency and large switching currents of the LP8758-EA make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 4 A per converter core, good power supply layout is much more difficult than most general PCB design. The following steps should be used as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range.

  1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the LP8758-EA VIN_Bx pin(s), as well as the trace between the input capacitor's negative node and power PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as tiny as possible for proper device operation.
  2. The output filter, consisting of Lx and COUTx, converts the switching signal at SW_Bx to the noiseless output voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the output capacitors of the device and the load (or input capacitors of the load) direct and wide to avoid losses due to the IR drop.
  3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close to the VANA pin as possible. VANA must be connected to the same power node as VIN_Bx pins.
  4. If the load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the load. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short and direct. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible.
  5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.

Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. Performing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process is strongly recommended, using a thermal modeling analysis software.