The power-up sequence for the LP8758-EA is as follows:
- VANA (and VIN_Bx) reach minimum recommended levels (V(VANA) > VANAUVLO).
- NRST is set to high level. This initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the LP8758-EA.
- The device enters STANDBY mode.
- The host can change the default register setting by I2C if needed.
- One or more of the converter cores can be enabled or disabled by one or more of the ENx pins and by the I2C interface.