SNVSC24 April 2021 LP8758-EA
When the input voltage falls below VANAUVLO at the VANA pin, the converter cores are disabled immediately, and the output capacitors are discharged using the pulldown resistors and the LP8758-EA device enters SHUTDOWN. When VANA voltage is above the UVLO threshold level and NRST signal is high, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (TOP_MASK.RESET_REG_MASK = 0) the INT_TOP.RESET_REG interrupt indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the INT_TOP.RESET_REG bit. If the host processor reads the INT_TOP.RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below UVLO level (or the host has requested reset), and the registers are reset to default values.