SLLSFX9A December   2024  – May 2025 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Control Profiles
          2. 7.3.8.5.2 Staircase Control Profiles
          3. 7.3.8.5.3 Forward-Reverse Profiles
          4. 7.3.8.5.4 Multi-Reference Mode Operation
          5. 7.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Control Mode
        5. 7.3.11.5 Current (Torque) Control Mode
        6. 7.3.11.6 Modulation Index Control
        7. 7.3.11.7 Overmodulation
        8. 7.3.11.8 Motor Speed Limit
        9. 7.3.11.9 Input DC Power Limit
      12. 7.3.12 Flux Weakening Control
      13. 7.3.13 Motor Parameters
        1. 7.3.13.1 Motor Resistance
        2. 7.3.13.2 Motor Inductance
        3. 7.3.13.3 Motor Back-EMF constant
      14. 7.3.14 Motor Parameter Extraction Tool (MPET)
      15. 7.3.15 Anti-Voltage Surge (AVS)
      16. 7.3.16 Active Braking
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 PWM Dithering
      19. 7.3.19 PWM Modulation Schemes
      20. 7.3.20 Dead Time Compensation
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 High-Side Braking
        5. 7.3.21.5 Active Spin-Down
      22. 7.3.22 Align Braking
      23. 7.3.23 FG Configuration
        1. 7.3.23.1 FG Output Frequency
        2. 7.3.23.2 FG during Open and Closed Loop States
        3. 7.3.23.3 FG during Fault and Idle States
      24. 7.3.24 Protections
        1. 7.3.24.1  VM Supply Undervoltage Lockout
        2. 7.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.24.5  Overvoltage Protection (OVP)
        6. 7.3.24.6  Overcurrent Protection (OCP)
          1. 7.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.24.7  Buck Overcurrent Protection
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled
        10. 7.3.24.10 Motor Lock Detection
          1. 7.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 7.3.24.11 Motor Lock (MTR_LCK)
          1. 7.3.24.11.1 MTR_LCK Latched Shutdown
          2. 7.3.24.11.2 MTR_LCK Automatic Recovery
          3. 7.3.24.11.3 MTR_LCK Report Only
          4. 7.3.24.11.4 MTR_LCK Disabled
        12. 7.3.24.12 EEPROM Fault
        13. 7.3.24.13 I2C CRC Fault
        14. 7.3.24.14 Minimum VM (Undervoltage) Protection
        15. 7.3.24.15 Maximum VM (Overvoltage) Protection
        16. 7.3.24.16 MPET Faults
        17. 7.3.24.17 IPD Faults
        18. 7.3.24.18 FET Thermal Warning (OTW)
        19. 7.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
        3. 7.6.1.3 EEPROM Security
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
  9. 8 EEPROM (Non-Volatile) Register Map
    1. 8.1 Algorithm_Configuration Registers
    2. 8.2 Fault_Configuration Registers
    3. 8.3 Hardware_Configuration Registers
    4. 8.4 Internal_Algorithm_Configuration Registers
  10. 9 RAM (Volatile) Register Map
    1. 9.1 Fault_Status Registers
    2. 9.2 System_Status Registers
    3. 9.3 Device_Control Registers
    4. 9.4 Algorithm_Control Registers
    5. 9.5 Algorithm_Variables Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Application Curves
        1. 10.2.1.1 Motor startup
        2. 10.2.1.2 MPET
        3. 10.2.1.3 Dead time compensation
        4. 10.2.1.4 Auto handoff
        5. 10.2.1.5 Anti voltage surge (AVS)
        6. 10.2.1.6 Real time variable tracking using DACOUT
    3. 10.3 UL Recognized Component: MCF8316DULVRGFR
      1. 10.3.1 IEC 60730 Functional Safety System
      2. 10.3.2 IEC 60730 Self Test Library (available only in MCF8316DULVRGFR)
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Bulk Capacitance
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
      3. 10.5.3 Thermal Considerations
        1. 10.5.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5 Algorithm_Variables Registers

Table 9-23 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 9-23 are considered as reserved locations and the register contents are not to be modified.

Table 9-23 ALGORITHM_VARIABLES Registers
OffsetAcronymRegister NameSection
18EhALGORITHM_STATECurrent Algorithm State RegisterSection 9.5.1
194hFG_SPEED_FDBKFG Speed Feedback RegisterSection 9.5.2
40ChBUS_CURRENTCalculated DC Bus Current RegisterSection 9.5.3
444hPHASE_CURRENT_AMeasured Current on Phase A RegisterSection 9.5.4
446hPHASE_CURRENT_BMeasured Current on Phase B RegisterSection 9.5.5
448hPHASE_CURRENT_CMeasured Current on Phase C RegisterSection 9.5.6
46AhIMAG_SQRSquare value of Motor phase peak currentSection 9.5.7
46ChCSA_GAIN_FEEDBACKCSA Gain RegisterSection 9.5.8
477hVOLTAGE_GAIN_FEEDBACKVoltage Gain RegisterSection 9.5.9
47ChVM_VOLTAGEVM Voltage RegisterSection 9.5.10
484hPHASE_VOLTAGE_VAPhase A Voltage RegisterSection 9.5.11
486hPHASE_VOLTAGE_VBPhase B Voltage RegisterSection 9.5.12
488hPHASE_VOLTAGE_VCPhase C Voltage RegisterSection 9.5.13
4BChSIN_COMMUTATION_ANGLESine of Commutation AngleSection 9.5.14
4BEhCOS_COMMUTATION_ANGLECosine of Commutation AngleSection 9.5.15
4DChIALPHAIALPHA Current RegisterSection 9.5.16
4DEhIBETAIBETA Current RegisterSection 9.5.17
4E0hVALPHAVALPHA Voltage RegisterSection 9.5.18
4E2hVBETAVBETA Voltage RegisterSection 9.5.19
4EChIDMeasured d-axis Current RegisterSection 9.5.20
4EEhIQMeasured q-axis Current RegisterSection 9.5.21
4F0hVDVD Voltage RegisterSection 9.5.22
4F2hVQVQ Voltage RegisterSection 9.5.23
52AhIQ_REF_ROTOR_ALIGNAlign Current ReferenceSection 9.5.24
540hSPEED_REF_OPEN_LOOPOpen Loop Speed RegisterSection 9.5.25
550hIQ_REF_OPEN_LOOPOpen Loop Current ReferenceSection 9.5.26
5D2hSPEED_REF_CLOSED_LOOPSpeed Reference RegisterSection 9.5.27
612hID_REF_CLOSED_LOOPReference for Current Loop RegisterSection 9.5.28
614hIQ_REF_CLOSED_LOOPReference for Current Loop RegisterSection 9.5.29
6AEhISD_STATEISD State RegisterSection 9.5.30
6B8hISD_SPEEDISD Speed RegisterSection 9.5.31
6EAhIPD_STATEIPD State RegisterSection 9.5.32
72EhIPD_ANGLECalculated IPD Angle RegisterSection 9.5.33
772hEDEstimated BEMF EQ RegisterSection 9.5.34
774hEQEstimated BEMF ED RegisterSection 9.5.35
782hSPEED_FDBKSpeed Feedback RegisterSection 9.5.36
786hTHETA_ESTEstimated rotor Position RegisterSection 9.5.37

Complex bit access types are encoded to fit into small table cells. Table 9-24 shows the codes that are used for access types in this section.

Table 9-24 Algorithm_Variables Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

9.5.1 ALGORITHM_STATE Register (Offset = 18Eh) [Reset = 0000h]

ALGORITHM_STATE is shown in Figure 9-15 and described in Table 9-25.

Return to the Summary Table.

Current Algorithm State Register

Figure 9-15 ALGORITHM_STATE Register
15141312111098
ALGORITHM_STATE
R-0h
76543210
ALGORITHM_STATE
R-0h
Table 9-25 ALGORITHM_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ALGORITHM_STATER0h 16-bit value indicating current state of device
  • 0h = MOTOR_IDLE
  • 1h = MOTOR_ISD
  • 2h = MOTOR_TRISTATE
  • 3h = MOTOR_BRAKE_ON_START
  • 4h = MOTOR_IPD
  • 5h = MOTOR_SLOW_FIRST_CYCLE
  • 6h = MOTOR_ALIGN
  • 7h = MOTOR_OPEN_LOOP
  • 8h = MOTOR_CLOSED_LOOP_UNALIGNED
  • 9h = MOTOR_CLOSED_LOOP_ALIGNED
  • Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING
  • Bh = MOTOR_SOFT_STOP
  • Ch = MOTOR_RECIRCULATE_STOP
  • Dh = MOTOR_BRAKE_ON_STOP
  • Eh = MOTOR_FAULT
  • Fh = MOTOR_MPET_MOTOR_STOP_CHECK
  • 10h = MOTOR_MPET_MOTOR_STOP_WAIT
  • 11h = MOTOR_MPET_MOTOR_BRAKE
  • 12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT
  • 13h = MOTOR_MPET_RL_MEASURE
  • 14h = MOTOR_MPET_KE_MEASURE
  • 15h = MOTOR_MPET_STALL_CURRENT_MEASURE
  • 16h = MOTOR_MPET_TORQUE_MODE
  • 17h = MOTOR_MPET_DONE
  • 18h = MOTOR_MPET_FAULT

9.5.2 FG_SPEED_FDBK Register (Offset = 194h) [Reset = 00000000h]

FG_SPEED_FDBK is shown in Figure 9-16 and described in Table 9-26.

Return to the Summary Table.

Speed Feedback from FG

Figure 9-16 FG_SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
FG_SPEED_FDBK
R-0h
Table 9-26 FG_SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0FG_SPEED_FDBKR0h 32-bit value indicating absolute (unsigned) value of estimated motor speed based on FG Estimated Motor Speed (in Hz) = (FG_SPEED_FDBK / 227) * MAX_SPEED (in Hz)

9.5.3 BUS_CURRENT Register (Offset = 40Ch) [Reset = 00000000h]

BUS_CURRENT is shown in Figure 9-17 and described in Table 9-27.

Return to the Summary Table.

Calculated Supply Current Register

Figure 9-17 BUS_CURRENT Register
313029282726252423222120191817161514131211109876543210
BUS_CURRENT
R-0h
Table 9-27 BUS_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
31-0BUS_CURRENTR0h 32-bit signed value indicating DC bus current. Negative value represented in two's complement. DC bus Current (in Amps) = (BUS_CURRENT / 227) * 10/8

9.5.4 PHASE_CURRENT_A Register (Offset = 444h) [Reset = 00000000h]

PHASE_CURRENT_A is shown in Figure 9-18 and described in Table 9-28.

Return to the Summary Table.

Measured current on Phase A Register

Figure 9-18 PHASE_CURRENT_A Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_A
R-0h
Table 9-28 PHASE_CURRENT_A Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_AR0h 32-bit signed value indicating measured continuous Phase A current. Negative value represented in two's complement. Phase A current (in Amps) = (PHASE_CURRENT_A / 227) * 10/8

9.5.5 PHASE_CURRENT_B Register (Offset = 446h) [Reset = 00000000h]

PHASE_CURRENT_B is shown in Figure 9-19 and described in Table 9-29.

Return to the Summary Table.

Measured current on Phase B Register

Figure 9-19 PHASE_CURRENT_B Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_B
R-0h
Table 9-29 PHASE_CURRENT_B Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_BR0h 32-bit signed value indicating measured continuous Phase B current. Negative value represented in two's complement. Phase B current (in Amps) = (PHASE_CURRENT_B / 227) * 10/8

9.5.6 PHASE_CURRENT_C Register (Offset = 448h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in Figure 9-20 and described in Table 9-30.

Return to the Summary Table.

Measured current on Phase C Register

Figure 9-20 PHASE_CURRENT_C Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_C
R-0h
Table 9-30 PHASE_CURRENT_C Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_CR0h 32-bit signed value indicating measured continuous Phase C current. Negative value represented in two's complement. Phase C current (in Amps) = (PHASE_CURRENT_C / 227) * 10/8

9.5.7 IMAG_SQR Register (Offset = 46Ah) [Reset = 00000000h]

IMAG_SQR is shown in Figure 9-21 and described in Table 9-31.

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Square value of Motor phase peak current

Figure 9-21 IMAG_SQR Register
313029282726252423222120191817161514131211109876543210
IMAG_SQR
R-0h
Table 9-31 IMAG_SQR Register Field Descriptions
BitFieldTypeResetDescription
31-0IMAG_SQRR0h 32-bit value indicating square value of motor phase peak current. Motor phase peak current (in A) = sqrt(IMAG_SQR/227)*10

9.5.8 CSA_GAIN_FEEDBACK Register (Offset = 46Ch) [Reset = 0000h]

CSA_GAIN_FEEDBACK is shown in Figure 9-22 and described in Table 9-32.

Return to the Summary Table.

VM Voltage Register

Figure 9-22 CSA_GAIN_FEEDBACK Register
15141312111098
CSA_GAIN_FEEDBACK
R-0h
76543210
CSA_GAIN_FEEDBACK
R-0h
Table 9-32 CSA_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0CSA_GAIN_FEEDBACKR0h 16-bit value indicating current sense gain. MIN_CSA_GAIN = 0.15V/A
  • 0h = MIN_CSA_GAIN * 8
  • 1h = MIN_CSA_GAIN * 4
  • 2h = MIN_CSA_GAIN * 2
  • 3h = MIN_CSA_GAIN * 1

9.5.9 VOLTAGE_GAIN_FEEDBACK Register (Offset = 477h) [Reset = 0000h]

VOLTAGE_GAIN_FEEDBACK is shown in Figure 9-23 and described in Table 9-33.

Return to the Summary Table.

Voltage Gain Register

Figure 9-23 VOLTAGE_GAIN_FEEDBACK Register
15141312111098
VOLTAGE_GAIN_FEEDBACK
R-0h
76543210
VOLTAGE_GAIN_FEEDBACK
R-0h
Table 9-33 VOLTAGE_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0VOLTAGE_GAIN_FEEDBACKR0h 16-bit value indicating voltage gain
  • 0h = 40V
  • 1h = 30V
  • 2h = 15V

9.5.10 VM_VOLTAGE Register (Offset = 47Ch) [Reset = 00000000h]

VM_VOLTAGE is shown in Figure 9-24 and described in Table 9-34.

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Supply voltage register

Figure 9-24 VM_VOLTAGE Register
313029282726252423222120191817161514131211109876543210
VM_VOLTAGE
R-0h
Table 9-34 VM_VOLTAGE Register Field Descriptions
BitFieldTypeResetDescription
31-0VM_VOLTAGER0h 32-bit value indicating DC bus voltage DC Bus Voltage (in Volts) = VM_VOLTAGE * 60 / 227

9.5.11 PHASE_VOLTAGE_VA Register (Offset = 484h) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in Figure 9-25 and described in Table 9-35.

Return to the Summary Table.

Phase A Voltage Register

Figure 9-25 PHASE_VOLTAGE_VA Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VA
R-0h
Table 9-35 PHASE_VOLTAGE_VA Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VAR0h 32-bit signed value indicating measured A phase voltage during ISD. Negative value represented in two's complement. Phase A voltage (in Volts) = PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 227)

9.5.12 PHASE_VOLTAGE_VB Register (Offset = 486h) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in Figure 9-26 and described in Table 9-36.

Return to the Summary Table.

Phase B Voltage Register

Figure 9-26 PHASE_VOLTAGE_VB Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VB
R-0h
Table 9-36 PHASE_VOLTAGE_VB Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VBR0h 32-bit signed value indicating measured B phase voltage during ISD. Negative value represented in two's complement. Phase B voltage (in Volts) = PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 227)

9.5.13 PHASE_VOLTAGE_VC Register (Offset = 488h) [Reset = 00000000h]

PHASE_VOLTAGE_VC is shown in Figure 9-27 and described in Table 9-37.

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Phase C Voltage Register

Figure 9-27 PHASE_VOLTAGE_VC Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VC
R-0h
Table 9-37 PHASE_VOLTAGE_VC Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VCR0h 32-bit signed value indicating measured C phase voltage during ISD. Negative value represented in two's complement. Phase C voltage (in Volts) = PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 227)

9.5.14 SIN_COMMUTATION_ANGLE Register (Offset = 4BCh) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in Figure 9-28 and described in Table 9-38.

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Sine of Commutation Angle

Figure 9-28 SIN_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
SIN_COMMUTATION_ANGLE
R-0h
Table 9-38 SIN_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIN_COMMUTATION_ANGLER0h 32-bit signed value indicating sine of rotor Angle. Negative value represented in two's complement. sin(rotor angle) = (SIN_COMMUTATION_ANGLE / 227)

9.5.15 COS_COMMUTATION_ANGLE Register (Offset = 4BEh) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in Figure 9-29 and described in Table 9-39.

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Cosine of Commutation Angle

Figure 9-29 COS_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
COS_COMMUTATION_ANGLE
R-0h
Table 9-39 COS_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0COS_COMMUTATION_ANGLER0h 32-bit signed value indicating cosine of rotor angle. Negative value represented in two's complement. cos(rotor angle) = (COS_COMMUTATION_ANGLE / 227)

9.5.16 IALPHA Register (Offset = 4DCh) [Reset = 00000000h]

IALPHA is shown in Figure 9-30 and described in Table 9-40.

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IALPHA Current Register

Figure 9-30 IALPHA Register
313029282726252423222120191817161514131211109876543210
IALPHA
R-0h
Table 9-40 IALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0IALPHAR0h 32-bit signed value indicating phase current in alpha- beta domain. Negative value represented in two's complement. IAlpha (in Amps) = (IALPHA / 227) * 10/8

9.5.17 IBETA Register (Offset = 4DEh) [Reset = 00000000h]

IBETA is shown in Figure 9-31 and described in Table 9-41.

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IBETA Current Register

Figure 9-31 IBETA Register
313029282726252423222120191817161514131211109876543210
IBETA
R-0h
Table 9-41 IBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0IBETAR0h 32-bit signed value indicating phase current in alpha- beta domain. Negative value represented in two's complement. IBeta (in Amps) = (IBETA / 227) * 10/8

9.5.18 VALPHA Register (Offset = 4E0h) [Reset = 00000000h]

VALPHA is shown in Figure 9-32 and described in Table 9-42.

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VALPHA Voltage Register

Figure 9-32 VALPHA Register
313029282726252423222120191817161514131211109876543210
VALPHA
R-0h
Table 9-42 VALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALPHAR0h 32-bit signed value indicating applied phase voltage in alpha-beta domain VAlpha (in Volts) = (VALPHA / 227) * 60 / sqrt(3)

9.5.19 VBETA Register (Offset = 4E2h) [Reset = 00000000h]

VBETA is shown in Figure 9-33 and described in Table 9-43.

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VBETA Voltage Register

Figure 9-33 VBETA Register
313029282726252423222120191817161514131211109876543210
VBETA
R-0h
Table 9-43 VBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0VBETAR0h 32-bit signed value indicating applied phase voltage in alpha-beta domain. Negative value represented in two's complement. VBeta (in Volts)) = (VBETA / 227) * 60 / sqrt(3)

9.5.20 ID Register (Offset = 4ECh) [Reset = 00000000h]

ID is shown in Figure 9-34 and described in Table 9-44.

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Measured d-axis Current Register

Figure 9-34 ID Register
313029282726252423222120191817161514131211109876543210
ID
R-0h
Table 9-44 ID Register Field Descriptions
BitFieldTypeResetDescription
31-0IDR0h 32-bit signed value indicating d-axis(flux component) phase current in d-q domain. Negative value represented in two's complement. Flux component phase current (in Amps) = (ID / 227) * 10/8

9.5.21 IQ Register (Offset = 4EEh) [Reset = 00000000h]

IQ is shown in Figure 9-35 and described in Table 9-45.

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Measured q-axis Current Register

Figure 9-35 IQ Register
313029282726252423222120191817161514131211109876543210
IQ
R-0h
Table 9-45 IQ Register Field Descriptions
BitFieldTypeResetDescription
31-0IQR0h 32-bit signed value indicating q-axis(torque component) phase current in d-q domain. Negative value represented in two's complement. Torque component phase current (in Amps) = (IQ / 227) * 10/8

9.5.22 VD Register (Offset = 4F0h) [Reset = 00000000h]

VD is shown in Figure 9-36 and described in Table 9-46.

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VD Voltage Register

Figure 9-36 VD Register
313029282726252423222120191817161514131211109876543210
VD
R-0h
Table 9-46 VD Register Field Descriptions
BitFieldTypeResetDescription
31-0VDR0h 32-bit signed value indicating applied phase voltage in d-q domain. Negative value represented in two's complement. Vd (in Volts) = (VD / 227) * 60 / sqrt(3)

9.5.23 VQ Register (Offset = 4F2h) [Reset = 00000000h]

VQ is shown in Figure 9-37 and described in Table 9-47.

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VQ Voltage Register

Figure 9-37 VQ Register
313029282726252423222120191817161514131211109876543210
VQ
R-0h
Table 9-47 VQ Register Field Descriptions
BitFieldTypeResetDescription
31-0VQR0h 32-bit signed value indicating applied phase voltage in d-q domain. Negative value represented in two's complement. Vq (in Volts) = (VQ / 227) * 60 / sqrt(3)

9.5.24 IQ_REF_ROTOR_ALIGN Register (Offset = 52Ah) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in Figure 9-38 and described in Table 9-48.

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Align Current Reference

Figure 9-38 IQ_REF_ROTOR_ALIGN Register
313029282726252423222120191817161514131211109876543210
IQ_REF_ROTOR_ALIGN
R-0h
Table 9-48 IQ_REF_ROTOR_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_ROTOR_ALIGNR0h 32-bit signed value indicating current reference during align state. Negative value represented in two's complement. Current reference during Align State (in Amps) = (IQ_REF_ROTOR_ALIGN / 227) * 10/8

9.5.25 SPEED_REF_OPEN_LOOP Register (Offset = 540h) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in Figure 9-39 and described in Table 9-49.

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Speed at which motor transitions to close loop

Figure 9-39 SPEED_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_OPEN_LOOP
R-0h
Table 9-49 SPEED_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_OPEN_LOOPR0h 32-bit signed value indicating open loop speed reference. Negative value represented in two's complement. Speed reference during open loop (in Hz) = (SPEED_REF_OPEN_LOOP / 227) * MAX_SPEED (in Hz)

9.5.26 IQ_REF_OPEN_LOOP Register (Offset = 550h) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in Figure 9-40 and described in Table 9-50.

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Open Loop Current Reference

Figure 9-40 IQ_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_OPEN_LOOP
R-0h
Table 9-50 IQ_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_OPEN_LOOPR0h 32-bit signed value indicating current reference during open loop. Negative value represented in two's complement. Current reference during open loop (in Amps) = (IQ_REF_OPEN_LOOP / 227) * 10/8

9.5.27 SPEED_REF_CLOSED_LOOP Register (Offset = 5D2h) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in Figure 9-41 and described in Table 9-51.

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Speed Reference Register

Figure 9-41 SPEED_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_CLOSED_LOOP
R-0h
Table 9-51 SPEED_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_CLOSED_LOOPR0h 32-bit signed value indicating reference for closed loop. Negative value represented in two's complement. In speed control mode, speed reference in closed loop (in Hz)= (SPEED_REF_CLOSED_LOOP/ 227) * MAX_SPEED (in Hz). In power mode, power reference in closed loop (in Watts) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_POWER (in Watts) In current mode, Iq current reference in closed loop (in Amps) = (SPEED_REF_CLOSED_LOOP / 227) * ILIMIT(in Amps)

9.5.28 ID_REF_CLOSED_LOOP Register (Offset = 612h) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in Figure 9-42 and described in Table 9-52.

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Reference for Current Loop Register

Figure 9-42 ID_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
ID_REF_CLOSED_LOOP
R-0h
Table 9-52 ID_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_REF_CLOSED_LOOPR0h 32-bit signed value indicating d-axis(flux component) phase current reference in closed loop . Negative value represented in two's complement. Flux component phase current reference in closed loop (in Amps) = (ID / 227) * 10/8

9.5.29 IQ_REF_CLOSED_LOOP Register (Offset = 614h) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in Figure 9-43 and described in Table 9-53.

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Reference for Current Loop Register

Figure 9-43 IQ_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_CLOSED_LOOP
R-0h
Table 9-53 IQ_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_CLOSED_LOOPR0h 32-bit signed value indicating q-axis(torque component) phase current reference in closed loop. Negative value represented in two's complement. Torque component phase current reference in closed loop (in Amps) = (IQ / 227) * 10/8

9.5.30 ISD_STATE Register (Offset = 6AEh) [Reset = 0000h]

ISD_STATE is shown in Figure 9-44 and described in Table 9-54.

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ISD state Register

Figure 9-44 ISD_STATE Register
15141312111098
ISD_STATE
R-0h
76543210
ISD_STATE
R-0h
Table 9-54 ISD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ISD_STATER0h 16-bit value indicating current ISD state
  • 0h = ISD_INIT
  • 1h = ISD_MOTOR_STOP_CHECK
  • 2h = ISD_ESTIM_INIT
  • 3h = ISD_RUN_MOTOR_CHECK
  • 4h = ISD_MOTOR_DIRECTION_CHECK
  • 5h = ISD_COMPLETE
  • 6h = ISD_FAULT

9.5.31 ISD_SPEED Register (Offset = 6B8h) [Reset = 00000000h]

ISD_SPEED is shown in Figure 9-45 and described in Table 9-55.

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ISD Speed Register

Figure 9-45 ISD_SPEED Register
313029282726252423222120191817161514131211109876543210
ISD_SPEED
R-0h
Table 9-55 ISD_SPEED Register Field Descriptions
BitFieldTypeResetDescription
31-0ISD_SPEEDR0h 32-bit value indicating calculated absolute speed during ISD state Speed estimated during ISD (in Hz) = (ISD_SPEED / 227) * MAX_SPEED (in Hz)

9.5.32 IPD_STATE Register (Offset = 6EAh) [Reset = 0000h]

IPD_STATE is shown in Figure 9-46 and described in Table 9-56.

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IPD state Register

Figure 9-46 IPD_STATE Register
15141312111098
IPD_STATE
R-0h
76543210
IPD_STATE
R-0h
Table 9-56 IPD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0IPD_STATER0h 16-bit value indicating current IPD state
  • 0h = IPD_INIT
  • 1h = IPD_VECTOR_CONFIG
  • 2h = IPD_RUN
  • 3h = IPD_SLOW_RISE_CLOCK
  • 4h = IPD_SLOW_FALL_CLOCK
  • 5h = IPD_WAIT_CURRENT_DECAY
  • 6h = IPD_GET_TIMES
  • 7h = IPD_SET_NEXT_VECTOR
  • 8h = IPD_CALC_SECTOR_RISE
  • 9h = IPD_CALC_ROTOR_POSITION
  • Ah = IPD_CALC_ANGLE
  • Bh = IPD_COMPLETE
  • Ch = IPD_FAULT

9.5.33 IPD_ANGLE Register (Offset = 72Eh) [Reset = 00000000h]

IPD_ANGLE is shown in Figure 9-47 and described in Table 9-57.

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Calculated IPD Angle Register

Figure 9-47 IPD_ANGLE Register
313029282726252423222120191817161514131211109876543210
IPD_ANGLE
R-0h
Table 9-57 IPD_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0IPD_ANGLER0h 32-bit signed value indicating measured IPD angle. Negative value represented in two's complement. IPD Angle (in degrees) = (IPD_ANGLE / 227) * 360

9.5.34 ED Register (Offset = 772h) [Reset = 00000000h]

ED is shown in Figure 9-48 and described in Table 9-58.

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Estimated BEMF EQ Register

Figure 9-48 ED Register
313029282726252423222120191817161514131211109876543210
ED
R-0h
Table 9-58 ED Register Field Descriptions
BitFieldTypeResetDescription
31-0EDR0h 32-bit signed value indicating estimated Back EMF along the D-Axis (Ed). Negative value represented in two's complement. Ed (in Volts) = (ED / 227) * 60 / sqrt(3)

9.5.35 EQ Register (Offset = 774h) [Reset = 00000000h]

EQ is shown in Figure 9-49 and described in Table 9-59.

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Estimated BEMF ED Register

Figure 9-49 EQ Register
313029282726252423222120191817161514131211109876543210
EQ
R-0h
Table 9-59 EQ Register Field Descriptions
BitFieldTypeResetDescription
31-0EQR0h 32-bit signed value indicating estimated Back EMF along the Q-Axis (Eq). Negative value represented in two's complement. Eq (in Volts) = (EQ / 227) * 60 / sqrt(3)

9.5.36 SPEED_FDBK Register (Offset = 782h) [Reset = 00000000h]

SPEED_FDBK is shown in Figure 9-50 and described in Table 9-60.

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Speed Feedback Register

Figure 9-50 SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
SPEED_FDBK
R-0h
Table 9-60 SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_FDBKR0h 32-bit signed value indicating estimated motor speed. Negative value represented in two's complement. Estimated Motor Speed (in Hz) = (SPEED_FDBK / 227) * MAX_SPEED (in Hz)

9.5.37 THETA_EST Register (Offset = 786h) [Reset = 00000000h]

THETA_EST is shown in Figure 9-51 and described in Table 9-61.

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Estimated rotor Position Register

Figure 9-51 THETA_EST Register
313029282726252423222120191817161514131211109876543210
THETA_EST
R-0h
Table 9-61 THETA_EST Register Field Descriptions
BitFieldTypeResetDescription
31-0THETA_ESTR0h 32-bit signed value indicating estimated rotor angle. Angle should be modulo 360 degrees. For example if the estimated Angle value 380 degrees then the value means 380%360 = 20 degrees Estimated rotor Angle (in degrees) = (THETA_EST / 227)*360