SLASEC4D May   2018  – December 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
      1.      Revision History
  2. 2Device Comparison
    1. 2.1 Related Products
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Pin Attributes
    3. 3.3 Signal Descriptions
    4. 3.4 Pin Multiplexing
    5. 3.5 Buffer Type
    6. 3.6 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Active Mode Supply Current Per MHz
    6. 4.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Production Distribution of LPM Supply Currents
    10. 4.10 Typical Characteristics - Current Consumption Per Module
    11. 4.11 Thermal Resistance Characteristics
    12. 4.12 Timing and Switching Characteristics
      1. 4.12.1  Power Supply Sequencing
        1. Table 4-1 PMM, SVS and BOR
      2. 4.12.2  Reset Timing
        1. Table 4-2 Wake-up Times From Low-Power Modes and Reset
      3. 4.12.3  Clock Specifications
        1. Table 4-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 4-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 4-5 DCO FLL, Frequency
        4. Table 4-6 DCO Frequency
        5. Table 4-7 REFO
        6. Table 4-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 4-9 Module Oscillator (MODOSC)
      4. 4.12.4  Internal Shared Reference
        1. Table 4-10 Internal Shared Reference
      5. 4.12.5  General-Purpose I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
      6. 4.12.6  Digital I/O Typical Characteristics
      7. 4.12.7  Timer_B
        1. Table 4-13 Timer_B
      8. 4.12.8  eUSCI
        1. Table 4-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 4-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 4-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 4-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 4-19 eUSCI (I2C Mode) Switching Characteristics
      9. 4.12.9  ADC
        1. Table 4-20 ADC, Power Supply and Input Range Conditions
        2. Table 4-21 ADC, Timing Parameters
        3. Table 4-22 ADC, Linearity Parameters
      10. 4.12.10 Enhanced Comparator (eCOMP)
        1. Table 4-23 eCOMP0
        2. Table 4-24 eCOMP1
      11. 4.12.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 4-25 SAC, OA
        2. Table 4-26 SAC, DAC
      12. 4.12.12 FRAM
        1. Table 4-27 FRAM
      13. 4.12.13 Emulation and Debug
        1. Table 4-28 JTAG, Spy-Bi-Wire Interface
        2. Table 4-29 JTAG, 4-Wire Interface
  5. 5Detailed Description
    1. 5.1  CPU
    2. 5.2  Operating Modes
    3. 5.3  Interrupt Vector Addresses
    4. 5.4  Memory Organization
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Standard Interface
    7. 5.7  Spy-Bi-Wire Interface (SBW)
    8. 5.8  FRAM
    9. 5.9  Memory Protection
    10. 5.10 Peripherals
      1. 5.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 5.10.2  Clock System (CS) and Clock Distribution
      3. 5.10.3  General-Purpose Input/Output Port (I/O)
      4. 5.10.4  Watchdog Timer (WDT)
      5. 5.10.5  System Module (SYS)
      6. 5.10.6  Cyclic Redundancy Check (CRC)
      7. 5.10.7  Interrupt Compare Controller (ICC)
      8. 5.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 5.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 5.10.10 Backup Memory (BKMEM)
      11. 5.10.11 Real-Time Clock (RTC) Counter
      12. 5.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 5.10.13 Enhanced Comparator
      14. 5.10.14 Manchester Function Module (MFM)
      15. 5.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 5.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 5.10.17 Cross-Chip Interconnection (SACx are MSP430FR235x Devices Only)
      18. 5.10.18 Embedded Emulation Module (EEM)
      19. 5.10.19 Peripheral File Map
    11. 5.11 Input/Output Diagrams
      1. 5.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 5.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 5.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 5.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 5.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 5.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Layout Guidelines
    3. 6.3 ROM Libraries
    4. 6.4 Typical Applications
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Embedded microcontroller
    • 16-bit RISC architecture up to 24 MHz
    • Extended temperature: –40°C to 105°C
    • Wide supply voltage range from 3.6 V down to 1.8 V (operational voltage is restricted by SVS levels, see VSVSH- and VSVSH+ in PMM, SVS and BOR)
  • Optimized low-power modes (at 3 V)
    • Active mode: 142 µA/MHz
    • Standby:
      • LPM3 with 32768-Hz crystal: 1.43 µA (with SVS enabled)
      • LPM3.5 with 32768-Hz crystal: 620 nA (with SVS enabled)
    • Shutdown (LPM4.5): 42 nA (with SVS disabled)
  • Low-power ferroelectric RAM (FRAM)
    • Up to 32KB of nonvolatile memory
    • Built-in error correction code (ECC)
    • Configurable write protection
    • Unified memory of program, constants, and storage
    • 1015 write cycle endurance
    • Radiation resistant and nonmagnetic
  • Ease of use
    • 20KB ROM library includes driver libraries and FFT libraries
  • High-performance analog
    • One 12-channel 12-bit analog-to-digital converter (ADC)
      • Internal shared reference (1.5, 2.0, or 2.5 V)
      • Sample-and-hold 200 ksps
    • Two enhanced comparators (eCOMP)
      • Integrated 6-bit digital-to-analog converter (DAC) as reference voltage
      • Programmable hysteresis
      • Configurable high-power and low-power modes
      • One with fast 100-ns response time
      • One with 1-µs response time with 1.5-µA low power
    • Four smart analog combo (SAC-L3) (MSP430FR235x devices only)
      • Supports General-Purpose Operational Amplifier (OA)
      • Rail-to-rail input and output
      • Multiple input selections
      • Configurable high-power and low-power modes
      • Configurable PGA mode supports
        • Noninverting mode: ×1, ×2, ×3, ×5, ×9, ×17, ×26, ×33
        • Inverting mode: ×1, ×2, ×4, ×8, ×16, ×25, ×32
      • Built-in 12-bit reference DAC for offset and bias settings
      • 12-bit voltage DAC mode with optional references
  • Intelligent digital peripherals
    • Three 16-bit timers with three capture/compare registers each (Timer_B3)
    • One 16-bit timer with seven capture/compare registers each (Timer_B7)
    • One 16-bit counter-only real-time clock counter (RTC)
    • 16-bit cyclic redundancy checker (CRC)
    • Interrupt compare controller (ICC) enabling nested hardware interrupts
    • 32-bit hardware multiplier (MPY32)
    • Manchester codec (MFM)
  • Enhanced serial communications
    • Two enhanced USCI_A (eUSCI_A) modules support UART, IrDA, and SPI
    • Two enhanced USCI_B (eUSCI_B) modules support SPI and I2C
  • Clock system (CS)
    • On-chip 32-kHz RC oscillator (REFO)
    • On-chip 24-MHz digitally controlled oscillator (DCO) with frequency locked loop (FLL)
      • ±1% accuracy with on-chip reference at room temperature
    • On-chip very low-frequency 10-kHz oscillator (VLO)
    • On-chip high-frequency modulation oscillator (MODOSC)
    • External 32-kHz crystal oscillator (LFXT)
    • External high-frequency crystal oscillator up to 24 MHz (HFXT)
    • Programmable MCLK prescaler of 1 to 128
    • SMCLK derived from MCLK with programmable prescaler of 1, 2, 4, or 8
  • General input/output and pin functionality
    • 44 I/Os on 48-pin package
    • 32 interrupt pins (P1, P2, P3, and P4) can wake MCU from LPMs
  • Development tools and software (also see Tools and Software)
  • Family members (also see Device Comparison)
    • MSP430FR2355: 32KB of program FRAM, 512 bytes of data FRAM, 4KB of RAM
    • MSP430FR2353: 16KB of program FRAM, 512 bytes of data FRAM, 2KB of RAM
    • MSP430FR2155: 32KB of program FRAM, 512 bytes of data FRAM, 4KB of RAM
    • MSP430FR2153: 16KB of program FRAM, 512 bytes of data FRAM, 2KB of RAM
  • Package options
    • 48-pin: LQFP (PT)
    • 40-pin: VQFN (RHA)
    • 38-pin: TSSOP (DBT)
    • 32-pin: VQFN (RSM)