TYP data are based on VCC = 3.0 V and TA = 25°C, unless otherwise noted
|VCC||Supply voltage range applied at all DVCC and AVCC pins(1) (2) (3)||1.8(6)||3.6||V|
|VSS||Supply voltage applied at all DVSS and AVSS pins.||0||V|
|TA||Operating free-air temperature||–40||85||°C|
|TJ||Operating junction temperature||–40||85||°C|
|CDVCC||Capacitor value at DVCC(4)||1–20%||µF|
|fSYSTEM||Processor frequency (maximum MCLK frequency)(5)||No FRAM wait states |
(NWAITSx = 0)
|0 ||8(8) ||MHz|
|With FRAM wait states |
(NWAITSx = 1)(7)
|0 ||16(9) |
|fACLK||Maximum ACLK frequency||50||kHz|
|fSMCLK||Maximum SMCLK frequency||16(9)||MHz|
(1) TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified under Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for capacitor CDVCC should limit the slopes accordingly.
(3) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(4) For each supply pin pair (DVCC and DVSS, AVCC and AVSS), place a low-ESR ceramic capacitor of 100 nF (minimum) as close as possible (within a few millimeters) to the respective pin pairs.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(6) The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.
(7) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted without wait states.
(8) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
(9) DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a higher typical value is used, the clock must be divided in the clock system.