SLASF12C February   2023  – October 2023 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 TRNG
      1. 7.20.1 TRNG Electrical Characteristics
      2. 7.20.2 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.17.1 SPI

over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
SPI
fSPI SPI clock frequency Clock max speed = 32MHz
1.62 < VDD < 3.6V
Controller mode		 16 MHz
fSPI SPI clock frequency Clock max speed = 32MHz
1.62 < VDD < 3.6V
Peripheral mode		 16 MHz
fSPI SPI clock frequency Clock max speed >= 32MHz
1.62 < VDD < 3.6V
Controller mode		 16 MHz
fSPI SPI clock frequency Clock max speed >= 48MHz
1.62 < VDD < 2.7V
Controller mode with High speed IO		 24 MHz
fSPI SPI clock frequency Clock max speed >= 64MHz
2.7 < VDD < 3.6V
Controller mode with High speed IO		 32 MHz
fSPI SPI clock frequency Clock max speed >= 32MHz
1.62 < VDD < 3.6V
Peripheral mode		 16 MHz
fSPI SPI clock frequency Clock max speed >= 48MHz
1.62 < VDD < 2.7V
Peripheral mode with High speed IO		 24 MHz
fSPI SPI clock frequency Clock max speed >= 64MHz
2.7 < VDD < 3.6V
Peripheral mode with High speed IO		 32 MHz
DCSCK SCK Duty Cycle 40 50 60 %
Controller
tSCLK_H/L SCLK High or Low time  (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns
tCS.LEAD CS lead-time, CS active to clock SPH=0 1 SPI Clock
tCS.LEAD CS lead-time, CS active to clock SPH=1 1/2 SPI Clock
tCS.LAG CS lag time, Last clock to CS inactive 1 SPI Clock
tCS.ACC CS access time, CS active to PICO data out 1/2 SPI Clock
tCS.DIS CS disable time, CS inactive to PICO high inpedance 1 SPI Clock
tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns
tSU.CI POCI input data setup time (1) 1.62 < VDD < 2.7V, delayed sampling enabled 1 ns
tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, no delayed sampling 29 ns
tSU.CI POCI input data setup time (1) 1.62 < VDD < 2.7V, no delayed sampling 37 ns
tHD.CI POCI input data hold time delayed sampling enabled 24 ns
tHD.CI POCI input data hold time no delayed sampling 0 ns
tVALID.CO PICO output data valid time (2) 10 ns
tHD.CO PICO output data hold time (3) 6 ns
Peripheral
tCS.LEAD CS lead-time, CS active to clock 11 ns
tCS.LAG CS lag time, Last clock to CS inactive 1 ns
tCS.ACC CS access time, CS active to POCI data out 26 ns
tCS.DIS CS disable time, CS inactive to POCI high inpedance 26 ns
tSU.PI PICO input data setup time 7 ns
tHD.PI PICO input data hold time 0 ns
tVALID.PO POCI output data valid time(2) 2.7 < VDD < 3.6V 25 ns
tVALID.PO POCI output data valid time(2) 1.62 < VDD < 2.7V 31 ns
tHD.PO POCI output data hold time(3) 5 ns
(1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.
(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge
(3) Specifies how long data on the output is valid after the output changing SCLK clock edge