SBOS982G June   2020  – July 2022 OPA2863 , OPA4863 , OPA863


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: OPA863
    5. 7.5  Thermal Information: OPA2863
    6. 7.6  Thermal Information: OPA4863
    7. 7.7  Electrical Characteristics: VS = 10 V
    8. 7.8  Electrical Characteristics: VS = 3 V
    9. 7.9  Typical Characteristics: VS = 10 V
    10. 7.10 Typical Characteristics: VS = 3 V
    11. 7.11 Typical Characteristics: VS = 3 V to 10 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Low-Side Current Sensing
      1. 9.2.1 Design Requirements
    3. 9.3 Front-End Gain and Filtering
    4. 9.4 Low-Power SAR ADC Driver and Reference Buffer
    5. 9.5 Variable Reference Generator Using MDAC
    6. 9.6 Clamp-On Ultrasonic Flow Meter
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Achieving optimum performance with a high-frequency amplifier (like the OPAx863 devices) require careful attention to board layout parasitics and external component types. The OPA2863 DGK Evaluation Module user's guide can be used as a reference when designing the circuit board. Recommendations that optimize performance includes the following:

  1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability on the noninverting input and can react with the source impedance to cause unintentional band-limiting. Open a window around the signal I/O pins in all of the ground and power planes around those pins to reduce unwanted capacitance. Otherwise, ground and power planes must be unbroken elsewhere on the board.
  2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency 0.01-µF decoupling capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These can be placed somewhat farther from the device and shared among several devices in the same area of the PC board.
  3. Careful selection and placement of external components preserve the high frequency performance of the OPAx863 devices. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Keep resistor values as low as possible and consistent with load driving considerations. Lowering the resistor values keep the resistor noise terms low and minimize the effect of its parasitic capacitance; lower resistor values, however, increase the dynamic power consumption because RF and RG become part of the amplifiers output load network.