SLES102B December 2003 – March 2015 PCM1798
The PCM1798 is a 24-bit, 192-kHz, differential current output DAC that comes in a 28-pin SSOP package. The PCM1798 is a hardware controlled and utilizes the advanced segment DAC architecture from TI in order to perform with a Stereo Dynamic Range of 123 dB (126 dB Mono) and SNR of 123 dB (126 dB Mono) with a THD of 0.0005%. The PCM1798 will use the SCK input as its system clock and automatically detect the sampling rate of the Digital Audio input and has a high tolerance for clock jitter. The internal filter can be bypassed to allow for an external digital filter to be used.
The PCM1798 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1798 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1798 system clock.
|SAMPLING FREQUENCY||SYSTEM CLOCK FREQUENCY (fSCK) (MHz)|
|128 fS||192 fS||256 fS||384 fS||512 fS||768 fS|
The PCM1798 includes a power-on reset function. Figure 2 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V.
The PCM1798 also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1798 to initialize to its default reset state.
Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1798 power up and system clock activation.
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1798 on the rising edge of BCK. LRCK is the serial audio left/right word clock.
The PCM1798 requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed.
The PCM1798 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 5, Figure 6, and Figure 7. Data formats are selected using FMT0 (pin 11) and FMT1 (pin 12) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 4 shows a detailed timing diagram for the serial audio interface.
Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1798 also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1798 can select the DF rolloff characteristics.
|0||1||1||1||Digital filter bypass||Mono||—|
|1||0||0||1||Left-justified format||Mono, L-channel||Sharp|
|1||0||1||0||Standard, 16-bit||Mono, L-channel||Sharp|
|1||0||1||1||Standard, 24-bit||Mono, L-channel||Sharp|
|1||1||0||1||Left-justified format||Mono, R-channel||Sharp|
|1||1||1||0||Standard, 16-bit||Mono, R-channel||Sharp|
|1||1||1||1||Standard, 24-bit||Mono, R-channel||Sharp|
The PCM1798 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. This system provides pop-free muting of the DAC output.
The PCM1798 has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled using DEM (pin 3).
When the PCM1798 detects that the audio input data in the L-channel and the R-channel is continuously zero for 1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024 WDCKs in the external filter mode, the PCM1798 sets ZERO (pin 13) to HIGH.
The PCM1798 is a hardware controlled device. The pins CHSL, DEM, FMT0, FMT1, MONO, and MUTE control the functionality of this part. See the Pin Functions table or the Feature Description section for more detail.