7.3.1 Hardware Control

The FMT0, FMT1, OSR, BYPASS, MD0, and MD1 pins allow the device to be controlled by tying these pins to GPIO and GND or VDD from a host IC. These controls allow full configuration of the PCM1802.

7.3.2 Power-On Reset Sequence

The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when the power supply (V_DD) exceeds 2.2 V (typical). While V_DD < 2.2 V (typical), and for 1024 system-clock counts after V_DD > 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 4480 / f_S is passed. Figure 22 illustrates the internal power-on reset timing and the digital output for power-on reset.

Figure 22. Internal Power-On Reset Timing

7.3.3 System Clock

The PCM1802 supports 256 f_S, 384 f_S, 512 f_S, and 768 f_S as the system clock, where f_S is the audio sampling frequency. The system clock must be supplied on SCKI.

The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at 256 f_S, 384 f_S, 512 f_S, or 768 f_S in slave mode. In master mode, the system clock frequency must be selected by MODE0 and MODE1, and 768 f_S is not available. For system clock inputs of 384 f_S, 512 f_S, and 768 f_S, the system clock is divided to 256 f_S automatically, and the 256 f_S clock operates the delta-sigma modulator and the digital filter.

Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Table 2 shows system clock timing.

7.4.1 Power Down, HPF Bypass, Oversampling Control

PDWN controls the entire ADC operation. During power-down mode, both the supply current for the analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized. DOUT is also disabled and no system clock is accepted during power-down mode.

The built-in function for DC component rejection can be bypassed using the BYPAS control. In bypass mode, the DC components of the analog input signal, such as the internal DC offset, are converted and included in the digital output data.

OSR controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is available for f_S < 50 kHz, and must be used carefully as the duty cycle of the 384 f_S system clock affects performance.

7.4.2 Serial Audio Data Interface

The PCM1802 interfaces with the audio system through BCK, LRCK, FSYNC, and DOUT.

7.4.2.2 Interface Timing

Figure 24 and Figure 26 illustrate the interface timing in slave mode and master mode, respectively.

Figure 23. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)

Timing measurement reference level is (V_IH + V_IL) / 2. Rise and fall times are measured from 10% to 90% of IN to OUT signal swing. Load capacitance of DOUT is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)

Table 7. Audio Data Interface Timing: Slave Mode

PARAMETER		MIN	MAX	UNIT
t(BCKP)	BCK period	150		ns
t(BCKH)	BCK pulse duration, high	60		ns
t(BCKL)	BCK pulse duration, low	60		ns
t(LRSU)	LRCK setup time to BCK rising edge	40		ns
t(LRHD)	LRCK hold time to BCK rising edge	20		ns
t(LRCP)	LRCK period	10		µs
t(FSSU)	FSYNC setup time to BCK rising edge	20		ns
t(FSHD)	FSYNC hold time to BCK rising edge	20		ns
t(CKDO)	Delay time, BCK falling edge to DOUT valid	–10	20	ns
t(LRDO)	Delay time, LRCK edge to DOUT valid	–10	20	ns
tr	Rise time of all signals		10	ns
tf	Fall time of all signals		10	ns

Figure 25. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)

Timing measurement reference level is (V_IH + V_IL) / 2. Rise and fall times are measured from 10% to 90% of IN to OUT signal swing. Load capacitance of all signals is 20 pF.

Figure 26. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Work as Outputs)

Table 8. Audio Data Interface Timing: Master Mode

PARAMETER		MIN	TYP	MAX	UNIT
t(BCKP)	BCK period	150	1 / (64 fS)	1200	ns
t(BCKH)	BCK pulse duration, high	75		600	ns
t(BCKL)	BCK pulse duration, low	75		600	ns
t(CKLR)	Delay time, BCK falling edge to LRCK valid	–10		20	ns
t(LRCP)	LRCK period	10	1 / fS	80	µs
t(CKFS)	Delay time, BCK falling edge to FSYNC valid	–10		20	ns
t(FSYP)	FSYNC period	5	1 / (2 fS)	40	µs
t(CKDO)	Delay time, BCK falling edge to DOUT valid	–10		20	ns
t(LRDO)	Delay time, LRCK edge to DOUT valid	–10		20	ns
tr	Rise time of all signals			10	ns
tf	Fall time of all signals			10	ns

7.4.2.3 Synchronization With Digital Audio System

In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.

If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 f_S BCK (±5 BCKs for 48 f_S BCK) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / f_S and digital output is forced into BPZ code until resynchronization between LRCK and SCKI is completed.

In the case of changes less than ±5 BCKs for 64 BCK per frame (±4 BCKs for 48 BCK per frame), resynchronization does not occur.

Figure 27 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, some noise might be generated in the audio signal. The transition of normal to undefined data and undefined or zero data to normal creates a data discontinuity in the digital output, which generates some noise in the audio signal.

TI recommends setting PDWN low to achieve stable analog performance when the sampling rate, interface mode, data format, or oversampling control is changed.

Figure 27. ADC Digital Output for Loss of Synchronization and Resynchronization

7.4.3 Master Mode

In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802. The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768-f_S system clock is not available in master mode.

7.4.4 Slave Mode

In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC enables the BCK signal, and the device can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-f_S BCK or the 48-f_S BCK format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-f_S BCK format and within 12 BCKs for the 48-f_S BCK format.

7.4.5 Interface Mode

The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 and MODE0 as shown in Table 9.

In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802 and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data transfer from an external controller.