SLES023D December   2001  – December 2016 PCM1802


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Typical Characteristics: Internal Filter
        1. Digital Filter: Decimation Filter Frequency Response
        2. HPF (High-Pass Filter) Frequency Response
        3. Analog Filter: Antialiasing Filter Frequence Response
      2. 6.6.2 Typical Characteristics: Output Spectrum
      3. 6.6.3 Typical Characteristics: Supply Current
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Power-On Reset Sequence
      3. 7.3.3 System Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down, HPF Bypass, Oversampling Control
      2. 7.4.2 Serial Audio Data Interface
        1. Data Format
        2. Interface Timing
        3. Synchronization With Digital Audio System
      3. 7.4.3 Master Mode
      4. 7.4.4 Slave Mode
      5. 7.4.5 Interface Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Control Pins
        2. DSP or Audio Processor
        3. Input Filters
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VCC and VDD Pins
      2. 10.1.2 AGND and DGND Pins
      3. 10.1.3 VIN Pins
      4. 10.1.4 VREF1 Pin
      5. 10.1.5 VREF2 Pin
      6. 10.1.6 DOUT Pin
      7. 10.1.7 System Clock
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

VCC and VDD Pins

The digital and analog power supply lines to the PCM1802 must be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC.

AGND and DGND Pins

To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected internally. These grounds must have low impedance to avoid digital noise feeding back into the analog ground. They must be connected directly to each other under the parts to reduce the potential noise problem.

VIN Pins

TI recommends a 1-µF capacitor for AC-coupling, which gives an 8-Hz cutoff frequency. A higher full-scale input voltage, if required, can be accommodated by adding only one series resistor to each VIN pin.


TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF1 and AGND to ensure low source impedance for the ADC references. These capacitors must be placed as close as possible to the VREF1 pin to reduce dynamic errors on the ADC references.


The differential voltage between VREF2 and AGND sets the analog input full-scale range. TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF2 and AGND with the insertion of a 1-kΩ resistor between VCC and VREF2 when using a noisy analog power supply. These capacitors and resistor are not required for a clean analog supply. These capacitors must be placed as close as possible to the VREF2 pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-kΩ resistor, decreasing by 3%.


The DOUT pin has enough load drive capability, but TI recommends placing a buffer near the PCM1802 and minimizing load capacitance if the DOUT line is long, to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC.

System Clock

The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time difference between the system clock transition and the BCK or LRCK transition.

Layout Example

PCM1802 PCM1802_layout_1.gif Figure 30. Layout Recommendation