illustrates an example of a PCB layout for a data acquisition system using the REF70.
Some key considerations are:
- Connect low-ESR, 0.1-μF ceramic
bypass capacitors at VIN of the REF70.
- Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.
- Decouple other active devices in
the system per the device specifications.
- Using a solid ground plane helps
distribute heat and reduces electromagnetic interference (EMI) noise
- Place the external components as
close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
- Do not run sensitive analog
traces in parallel with digital traces. Avoid crossing digital and analog traces
if possible, and only make perpendicular crossings when absolutely