SLLS881G December   2007  – October 2014 SN65LVDS315

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Device Electrical Characteristics
    6. 6.6 Output Electrical Characteristics
    7. 6.7 Input Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Blanking Power Consumption Test Pattern
    2. 7.2 Maximum Power Consumption Test Pattern
    3. 7.3 Jitter Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Frame Counter Size
      2. 8.3.2 Data Formats
      3. 8.3.3 Parallel Input Port Timing Information
      4. 8.3.4 MIPI CSI-1 / CCP2-Class 0 Interface
      5. 8.3.5 Frame Structure and Synchronization Codes
      6. 8.3.6 Preventing Wrong Synchronization
      7. 8.3.7 Frame Structure
      8. 8.3.8 VS and HS Timing to Generate the Correct Control Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powerdown Modes
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Standby Mode
      2. 8.4.2 Active Modes
        1. 8.4.2.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.2.2 Transmit Mode
      3. 8.4.3 Status Detect and Operating Modes Flow Diagram
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Receiver Termination Requirement
      2. 9.1.2 Preventing Control Inputs From Increased Leakage Currents
    2. 9.2 Typical Application
      1. 9.2.1 VGA Camera Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Calculation Example: VGA Camera Sensor
          2. 9.2.1.2.2 Typical Application Frequencies
            1. 9.2.1.2.2.1 8-Bit Camera Application
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

io_v_lls881.gifFigure 7. I/O Voltage and Current Definition
sig_setup_lls881.gifFigure 8. Input Signal Setup and Hold Time Definition TDS And TDH
hold_t_def_lls881.gifFigure 9. Output Signal Setup and Hold Time Definition Ts(DOUT) And Th(DOUT)
rise_fall_t_lls881.gifFigure 10. Rise and Fall Time Definition
dvr_op_v_lls881.gifFigure 11. Driver Output Voltage Test Circuit and Definitions
prop_dly_lls881.gifFigure 12. TPD(L) Propagation Delay Input to Output
pwr_tst_lls881.gifFigure 13. Power Supply Noise Test Set-Up
glitch_sup_lls881.gifFigure 14. Glitch Suppression Enable/Disable Time
standby_lls881.gifFigure 15. Standby Detection

7.1 Typical Blanking Power Consumption Test Pattern

During blanking VS is low, and the SN65LVDS315 data output DOUT presents a high signal. The typical power consumption test patterns during the blanking time consists of one data word. The pattern repeats itself throughout the entire measurement.

Table 1. Typical IC Power Consumption Test During Blanking

WORD TEST PATTERN
D[7:0] VS HS
1 0x00 0 x

7.2 Maximum Power Consumption Test Pattern

The maximum (or worst-case) power consumption of the SN65LVDS315 is tested using an alternating 1010 test pattern. The pattern repeats itself throughout the entire measurement.

Table 2. Worst Case IC Power Consumption Test Pattern 1

WORD TEST PATTERN
D[7:0] VS HS
1 0x00 1 1
2 0xFF 1 1

7.3 Jitter Performance

The jitter performance of the SN65LVDS315 is tested using a pattern that stresses the interconnect, particularly to test for ISI. The test pattern uses very long run lengths of consecutive bits. The pattern incorporates very high and low data rates, and maximizes switching noise. The pattern is self-repeating for the duration of the test.

Table 3. Jitter Test Pattern

WORD TEST PATTERN
D[7:0] VS HS
1 0x00 1 1
2 0x00 1 1
3 0x00 1 1
4 0x01 1 1
5 0x03 1 1
6 0x07 1 1
7 0x18 1 1
8 0xE7 1 1
9 0x35 1 1
10 0x02 1 1
11 0x54 1 1
12 0xA5 1 1
13 0xAD 1 1
14 0x55 1 1
15 0xA6 1 1
16 0xA6 1 1
17 0x55 1 1
18 0x55 1 1
19 0xAA 1 1
20 0x52 1 1
21 0x5A 1 1
22 0xAB 1 1
23 0xFD 1 1
24 0xCA 1 1
25 0x18 1 1
26 0xE7 1 1
27 0xF8 1 1
28 0xFC 1 1
29 0xFE 1 1
30 0xFF 1 1
31 0xFF 1 1
32 0xFF 1 1