SLVSJX2 September   2025 SN74ACT2G101-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
      3. 7.3.3 Wettable Flanks
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

SN74ACT2G101-Q1 BQB Package,16-Pin WQFN(Top View)Figure 4-1 BQB Package,16-Pin WQFN(Top View)
SN74ACT2G101-Q1 PW Package,16-Pin TSSOP(Top View)Figure 4-2 PW Package,16-Pin TSSOP(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
CLR1 1 I Channel 1, clear, active low
CLKA1 2 I Channel 1, clock input A
CLKB1 3 I Channel 1, clock input B
CLKC1 4 I Channel 1, clock input C
CLKD1 5 I Channel 1, clock input D
Q1 6 O Channel 1, non-inverted output
D1 7 I Channel 1, data input
GND 8 G Ground
D2 9 I Channel 2, data input
Q2 10 O Channel 2, non-inverted output
CLKD2 11 I Channel 2, clock input D
CLKC2 12 I Channel 2, clock input C
CLKB2 13 I Channel 2, clock input B
CLKA2 14 I Channel 2, clock input A
CLR2 15 I Channel 2, clear, active low
VCC 16 P Positive supply
Thermal Pad(2) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) BQB package only