SLVSJX2 September   2025 SN74ACT2G101-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4.   4
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
      3. 7.3.3 Wettable Flanks
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
fclock Clock frequency 5V ± 0.5V 120 MHz
tW Pulse duration CLR low 5V ± 0.5V 4 ns
CLKx 5V ± 0.5V 4
tSU Set up time D before any CLKx 5V ± 0.5V 5 ns
CLR high before any CLKx 5V ± 0.5V 0 ns
tCLKX_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 5V ± 0.5V 8 ns
CLKB input pin relative to CLKA, CLKC and CLKD pins 5V ± 0.5V 4 ns
CLKC input pin relative to CLKA, CLKB and CLKD pins 5V ± 0.5V 4 ns
CLKD input pin relative to CLKA, CLKB and CLKC pins 5V ± 0.5V 4 ns
tH Hold time D before any CLKx 5V ± 0.5V 4 ns